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 José Ángel Gregorio

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Average citations per article5.11
Citation Count194
Publication count38
Publication years1992-2016
Available for download12
Average downloads per article398.58
Downloads (cumulative)4,783
Downloads (12 Months)137
Downloads (6 Weeks)18
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38 results found Export Results: bibtexendnoteacmrefcsv

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1
January 2016 IEEE Transactions on Parallel and Distributed Systems: Volume 27 Issue 1, January 2016
Publisher: IEEE Press
Bibliometrics:
Citation Count: 1

This work shows how by adapting replacement policies in contemporary cache hierarchies it is possible to extend the lifespan of a write endurance-limited main memory by almost one order of magnitude. The inception of this idea is that during cache residency 1) blocks are modified in a bimodal way: either ...

2
November 2015 Parallel Computing: Volume 49 Issue C, November 2015
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 0

We show the high variability in last-level cache access patterns.When applications interact, current dynamic policies have not enough flexibility.We present MIP, a replacement policy based on mobile insertion position.MIP rapidly adapts to sudden changes in access patterns during application runtime.Our solution provides 30% better hit-rate than LRU and 10% than ...
Keywords: Cache hierarchy, Replacement policy, Multiprocessor, Last level cache

3
September 2013 DSD '13: Proceedings of the 2013 Euromicro Conference on Digital System Design
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Computer architectures have evolved to structures where communication has become an essential part of the system and most of it currently takes place inside the chip. The number of on-Chip cores and the available off-chip bandwidth is not growing at the same rate. This demands for the inclusion of more ...
Keywords: Network on Chip, Routing, Cache Coherence, Chip Multiprocessor

4 published by ACM
January 2013 ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers: Volume 9 Issue 4, January 2013
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 2,   Downloads (12 Months): 23,   Downloads (Overall): 334

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Although abstraction is the best approach to deal with computing system complexity, sometimes implementation details should be considered. Considering on-chip interconnection networks in particular, underestimating the underlying system specificity could have nonnegligible impact on performance, cost, or correctness. This article presents a very efficient router that has been devised to ...
Keywords: cache-coherent CMP, Router microarchitecture, network on Chip

5
November 2012 IEEE Transactions on Parallel and Distributed Systems: Volume 23 Issue 11, November 2012
Publisher: IEEE Press
Bibliometrics:
Citation Count: 0

Multidestination communications are a highly necessary capability for many coherence protocols in order to minimize on-chip hit latency. Although CMPs share this necessity, up to now few suitable proposals have been developed. The combination of resource scarcity and the common idea that multicast support requires a substantial amount of extra ...
Keywords: Routing,System recovery,Unicast,Proposals,Protocols,Hardware,Vectors,router microarchitecture,Chip multiprocessor (CMP),multicast and broadcast communications,network-on-chip

6 published by ACM
May 2012 CF '12: Proceedings of the 9th conference on Computing Frontiers
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 2,   Downloads (12 Months): 17,   Downloads (Overall): 148

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This paper describes how on-chip network particularities could be used to improve coherence protocol responsiveness. In order to achieve this, a new coherence protocol, named LOCKE, is proposed. LOCKE successfully exploits large on-chip bandwidth availability to improve cache-coherent chip multiprocessor performance and energy efficiency. Provided that the interconnection network is ...
Keywords: cmp, coherence protocol, memory hierarchy

7
May 2012 NOCS '12: Proceedings of the 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 11

As in other computer architecture areas, interconnection networks research relies most of the times on simulation tools. This paper announces the release of an open-source tool suitable to be used for accurate modeling from small CMP to large supercomputer interconnection networks. The cycle-accurate modeling of TOPAZ can be used standalone ...
Keywords: simulator, interconnection networks, chip multiprocessor, supercomputer

8
March 2012 IEEE Transactions on Parallel and Distributed Systems: Volume 23 Issue 3, March 2012
Publisher: IEEE Press
Bibliometrics:
Citation Count: 0

This paper presents an innovative router design, called Rotary Router, which successfully addresses CMP cost/performance constraints. The router structure is based on two independent rings, which force packets to circulate either clockwise or counterclockwise, traveling through every port of the router. These two rings constitute a completely decentralized arbitration scheme ...
Keywords: Rotary Router, router architecture, interconnection networks, chip multiprocessors, coherence protocol, routing deadlock, coherence protocol deadlock.

9
July 2011 IEEE Computer Architecture Letters: Volume 10 Issue 2, July 2011
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

This paper presents a simple analytical model for predicting on-chip cache hierarchy effectiveness in chip multiprocessors (CMP) for a state-of-the-art architecture. Given the complexity of this type of systems, we use rough approximations, such as the empirical observation that the re-reference timing pattern follows a power law and the assumption ...
Keywords: Multi-core/single-chip multiprocessors, Memory hierarchy

10
December 2008 IEEE Transactions on Computers: Volume 57 Issue 12, December 2008
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 4

A complete mechanism for tolerating multiple failures in parallel computer systems, denoted as Immunet, is described in this paper. Immunet can be applied to arbitrary topologies, either regular or irregular, exhibiting in both cases graceful performance degradation. Provided that the network remains connected, Immunet is able to deal with any ...
Keywords: Parallel Architectures, Parallel Architectures, Interconnection architectures, Support for reliability, Support for reliability, Interconnection architectures

11 published by ACM
May 2008 ACM SIGARCH Computer Architecture News: Volume 36 Issue 2, May 2008
Publisher: ACM
Bibliometrics:
Citation Count: 5
Downloads (6 Weeks): 2,   Downloads (12 Months): 12,   Downloads (Overall): 350

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This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces a feasible way to allocate cache blocks according to the access pattern. Each L2 bank is dynamically partitioned at set level in private and ...

12
April 2008 NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 0,   Downloads (12 Months): 1,   Downloads (Overall): 63

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This paper introduces a cost-effective technique to deal with CMP coherence protocol requirements from the interconnection network point of view. A mechanism is presented to avoid the end-to-end deadlock that arises from the dependency chains created at the network interfaces between the different message types handled by coherence protocols. Our ...
Keywords: Router Design, Chip Multiprocessors, Deadlock

13
March 2008 Performance Evaluation: Volume 65 Issue 3-4, March, 2008
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 7

Interconnection networks in current parallel systems do not only increase in size; their buffer capacity and number of source ports have increased as well. All these factors result in a significant rise of network congestion compared with their predecessors. Consequently, packet injection must be restricted in order to prevent throughput ...
Keywords: Congestion control, Synchronized workload, Adaptive routing, Interconnection networks, Virtual cut-through

14 published by ACM
June 2007 ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture
Publisher: ACM
Bibliometrics:
Citation Count: 19
Downloads (6 Weeks): 2,   Downloads (12 Months): 41,   Downloads (Overall): 1,374

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The trend towards increasing the number of processor cores and cache capacity in future Chip-Multiprocessors (CMPs), will require scalable packet-switched interconnection networks adapted to the restrictions imposed by the CMP environment. This paper presents an innovative router design, which successfully addresses CMP cost/performance constraints. The router structure is based on ...
Keywords: chip multi-processors, router architecture, interconnection networks
Also published in:
June 2007  ACM SIGARCH Computer Architecture News: Volume 35 Issue 2, May 2007

15
June 2007 IEEE Transactions on Parallel and Distributed Systems: Volume 18 Issue 6, June 2007
Publisher: IEEE Press
Bibliometrics:
Citation Count: 5

This work presents Immucube, a scalable and efficient mechanism to improve dependability of interconnection networks for parallel and distributed computers. Immucube achieves better flexibility and scalability than any other previous fault-tolerant mechanism in k-ary n-cubes. The proposal inherits from Immunet several advantages over other previous fault-tolerant routing algorithms: 1) allowing ...
Keywords: Interconnection networks, fault-tolerant routing, k{\hbox{-}}aryn{\hbox{-}}cubes., Interconnection networks, fault-tolerant routing, k{hbox{-}}aryn{hbox{-}}cubes.

16
August 2006 Euro-Par'06: Proceedings of the 12th international conference on Parallel Processing
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 0

Welcome to the Euro-Par 2006 Topic 13 on Routing and Communication in Interconnection Networks. Interconnection networks is a key area in the quest for performance in parallel and distributed computers, and this topic is dedicated to techniques that improve the state of the art in interconnecting parallel computers, workstations or ...

17
June 2006 Journal of Systems Architecture: the EUROMICRO Journal: Volume 52 Issue 6, June 2006
Publisher: Elsevier North-Holland, Inc.
Bibliometrics:
Citation Count: 3

A strategy to implement adaptive routing in irregular networks is presented and analyzed in this work. A simple and widely applicable deadlock avoidance method, applied to a ring embedded in the network topology, constitutes the basis of this high-performance packet switching. This adaptive router improves the network capabilities by allocating ...
Keywords: deadlock, flow control, irregular topologies, networks of workstations, routing, cluster computing, local area networks

18
February 2006 PDP '06: Proceedings of the 14th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

Recent parallel systems use multiple injection ports and various injection policies, but little is known about their impact on network performance. This paper evaluates the influence that these injection interfaces have on maximum sustained throughput in adaptive cut-through torus networks by modeling the number of injection queues (1 or 4), ...

19 published by ACM
June 2004 WMPI '04: Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 1,   Downloads (12 Months): 9,   Downloads (Overall): 166

Full text available: PDFPDF
The ever increasing gap in processor and memory speeds has a very negative impact on performance. One possible solution to overcome this problem is the Kilo-instruction processor. It is a recent proposed architecture able to hide large memory latencies by having thousands of in-flight instructions. Current multiprocessor systems also have ...
Keywords: memory wall, CC-NUMA, ROB, shared-memory multiprocessors, instruction window, kilo-instruction processors

20 published by ACM
April 2004 CF '04: Proceedings of the 1st conference on Computing frontiers
Publisher: ACM
Bibliometrics:
Citation Count: 5
Downloads (6 Weeks): 1,   Downloads (12 Months): 4,   Downloads (Overall): 459

Full text available: PDFPDF
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be more severe in future processor's generation. Modern cache organizations and prefetching techniques will not be able to solve this problem. A ...
Keywords: ROB, in-flight instructions, shared-memory multiprocessors, Kilo-instruction processors, instruction window, memory wall, CC-NUMA



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