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 Emmanuel Casseau

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Average citations per article1.93
Citation Count56
Publication count29
Publication years1996-2018
Available for download5
Average downloads per article315.20
Downloads (cumulative)1,576
Downloads (12 Months)19
Downloads (6 Weeks)2
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29 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
May 2018 SCOPES '18: Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 16,   Downloads (Overall): 23

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This paper is aimed at studying fault-tolerant design of the realtime multi-processor systems and is in particular concerned with the dynamic mapping and scheduling of tasks on embedded systems. The effort is concentrated on scheduling strategy having reduced complexity and guaranteeing that, when a task is input into the system ...
Keywords: Primary/backup approach, Fault-tolerance, Low complexity, Dynamic scheduling, Homogeneous faulty processors, Multiprocessors

2
May 2017 Journal of Systems Architecture: the EUROMICRO Journal: Volume 76 Issue C, May 2017
Publisher: Elsevier North-Holland, Inc.
Bibliometrics:
Citation Count: 0

With the ability of customization for an application domain, extensible processors have been used more and more in embedded systems in recent years. Extensible processors customize an application domain by executing parts of application code in hardware instead of software. Determining parts of application code as custom instruction generally requires ...
Keywords: Subgraph selection algorithm, Custom instruction, Parallel algorithms, Extensible processors, Subgraph enumeration algorithm

3
August 2016 Microprocessors & Microsystems: Volume 45 Issue PA, August 2016
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 0

Extensible processors with custom function units (CFU) that implement parts of the application code can make good trade-off between performance and flexibility. In general, deciding profitable parts of the application source code that run on CFU involves two crucial steps: subgraph enumeration and subgraph selection. In this paper, we focus ...
Keywords: Custom instructions, Custom function units, Extensible processors, Data-flow graph, Heuristic algorithms

4
July 2015 Journal of Signal Processing Systems: Volume 80 Issue 1, July 2015
Publisher: Kluwer Academic Publishers
Bibliometrics:
Citation Count: 2

Multimedia applications and embedded platforms are both becoming very complex in order to improve user experience. Thus, multimedia developers need high-level methods to automate time-consuming and error-prone tasks. Dynamic dataflow modeling is attractive to describe complex applications, such as video codecs, at a high level of abstraction. This paper presents ...
Keywords: HEVC, Dataflow programming, Video coding, Embedded system

5
November 2014 Microprocessors & Microsystems: Volume 38 Issue 8, November 2014
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 0

The application-specific instruction set processors (ASIPs) have received more and more attention in recent years. ASIPs make trade-offs between flexibility and performance by extending the base instruction set of a general-purpose processor with custom functional units (CFUs). Custom instructions, executed on CFUs, make it possible to improve performance and achieve ...
Keywords: Custom instruction enumeration, DFG, Custom instruction selection, Extensible processors, ASIPs, Custom instruction

6
November 2013 Image Communication: Volume 28 Issue 10, November, 2013
Publisher: Elsevier Science Inc.
Bibliometrics:
Citation Count: 1

Modern embedded systems show a clear trend towards the use of Multiprocessor System-on-Chip (MPSoC) architectures in order to handle the performance and power consumption constraints. However, the design and validation of dedicated MPSoCs is an extremely hard and expensive task due to their complexity. Thus, the development of automated design ...
Keywords: Transport-Trigger Architecture (TTA), Dataflow programming, Reconfigurable Video Coding (RVC), Co-design, Multi-Processor System-on-Chip (MPSoC)

7
June 2012 Integration, the VLSI Journal: Volume 45 Issue 3, June, 2012
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 2

In recent years, the use of extensible processors has been increased. Extensible processors extend the base instruction set of a general-purpose processor with a set of custom instructions. Custom instructions that can be implemented in special hardware units make it possible to improve performance and decrease power consumption in extensible ...
Keywords: ASIPs, Custom instruction, Custom instruction generation algorithm, DFG, Extensible processors

8
January 2012 Integration, the VLSI Journal: Volume 45 Issue 1, January, 2012
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 3

In a mobile society, more and more devices need to continuously adapt to changing environments. Such mode switches can be smoothly done in software using a general purpose processor or a digital signal processor. However hardware cores only can cope with both throughput and power consumption constraints. Reconfigurable hardware platforms ...
Keywords: High-level synthesis, CAD, VLSI design

9
January 2012 International Journal of Embedded and Real-Time Communication Systems: Volume 3 Issue 1, January 2012
Publisher: IGI Global
Bibliometrics:
Citation Count: 0

This article presents an integrated environment for application scheduling, binding and routing used for the run-time reconfigurable, operator based, ROMA multimedia architecture. The environment is very flexible and after a minor modification can support other reconfigurable architectures. Currently, it supports the architecture model composed of a bank of single double ...
Keywords: Constraint Programming, Reconfigurable Data-Path, Scheduling, Binding, Compilation for Reconfigurable Architecture, Embedded Platform for Multimedia, Routing

10
September 2011 ASAP '11: Proceedings of the ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

In recent years, the use of extensible processors has been increased. Extensible processors extend the base instruction set of a general-purpose processor with a set of custom instructions. Custom instructions that can be implemented in special hardware units make it possible to improve performance and decrease power consumption in extensible ...
Keywords: magnitude speedup, custom instruction enumeration, extensible processors, base instruction set, general purpose processor, power consumption, high level application code

11 published by ACM
May 2011 GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Publisher: ACM
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 0,   Downloads (12 Months): 0,   Downloads (Overall): 179

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In order to meet growing market demands in flexibility and performance, the use of extensible processors has been increased. Extensible processors extend the base instruction set of a general-purpose processor with a set of custom instructions. Custom instruction that can be implemented in special hardware unit is a vital component ...
Keywords: custom instruction, DFG, custom instruction generation algorithm, extensible processors, ASIPs

12
March 2011 Journal of Signal Processing Systems: Volume 62 Issue 3, March 2011
Publisher: Kluwer Academic Publishers
Bibliometrics:
Citation Count: 1

Multimedia applications such as video and image processing are often characterized as computation intensive applications. For these applications the word-length of data and instructions is different throughout the application. Generating hardware architectures is not a straightforward task since it requires a deep word-length analysis in order to properly determine what ...
Keywords: Resource sharing, Hardware design, High-level synthesis, Data sizing

13
November 2010 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Volume 29 Issue 11, November 2010
Publisher: IEEE Press
Bibliometrics:
Citation Count: 2

This paper addresses the design of multimode architectures for digital signal and image processing applications. We present a dedicated design flow and its associated high-level synthesis tool, named GAUT. Given a unified description of a set of time-wise mutually exclusive tasks and their associated throughput constraints, a single register transfer ...
Keywords: allocation, binding, high-level synthesis (HLS), scheduling, Allocation, multimode architectures

14
July 2009 SAMOS'09: Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Publisher: IEEE Press
Bibliometrics:
Citation Count: 3

High-level synthesis (HLS) currently seems to be an interesting process to reduce the design time substantially. HLS tools actually map algorithms to architectures. While such tools were developed targeting ASIC technologies, HLS currently draws wide interest for FPGA designers. However with most of HLS techniques, traditional resource sharing models are ...
Keywords: CAD, VLSI design, component, high-level synthesis, FPGA

15
July 2009 ASAP '09: Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

For performance enhancement, reconfigurable processors have to overcome the overheads of reconfigurations such as the complexity of the interconnection network and reconfiguration time. In processors dealing with multimedia applications these overheads can be reduced by providing the reconfigurability inside the processing units rather than at interconnection level. Due to the ...
Keywords: multimedia processing, data level parallelism, reconfigurable systems, embedded systems

16
March 2009 ARC '09: Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 1

Image processing applications need embedded devices that can integrate evolutionary standards or various standards, that is to say devices have to be flexible to implement different algorithms at different times. In other respects these devices are constrained with stringent power requirements as well as high performance. Reconfigurable processor can address ...

17
November 2008 IEEE Transactions on Very Large Scale Integration (VLSI) Systems: Volume 16 Issue 11, November 2008
Publisher: IEEE Educational Activities Department
Bibliometrics:
Citation Count: 7

Multimedia applications such as video and image processing are often characterized by a huge number of data accesses. In many digital signal processing applications, array access patterns are regular and periodic. In these cases, optimized architectures using pipelined memory access controllers can be generated. In this paper, we focus on ...
Keywords: Graph model, graph model, high-level synthesis, memory sequencer, multimedia applications

18
November 2007 ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Publisher: IEEE Press
Bibliometrics:
Citation Count: 10
Downloads (6 Weeks): 0,   Downloads (12 Months): 1,   Downloads (Overall): 240

Full text available: PDFPDF
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis tool, named GAUT. Given a unified description of a set of time-wise mutually exclusive tasks and their associated throughput constraints, a single RTL hardware architecture optimized ...
Keywords: flexible devices, high-level synthesis, multi-mode architectures

19
August 2007 AHS '07: Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

In this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. The inputs of the design flow are the data flow graphs (DFGs), representing the different modes (i.e. the different applications to be implemented), with their respective throughput constraints. ...

20
February 2007 Integration, the VLSI Journal: Volume 40 Issue 2, February, 2007
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 0

In the system on chip design context, RTL design of complex digital signal processing coprocessors can be improved by using algorithmic description as input for the synthesis process. System integration, that is a major step in SoC design, requires taking into account communication and timing constraints to design and integrate ...
Keywords: MAP algorithm, Hardware optimization, DSP applications, IP design and integration, Real-time SoC design



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