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 Sreenivas Subramoney

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Average citations per article6.86
Citation Count96
Publication count14
Publication years2000-2018
Available for download14
Average downloads per article356.00
Downloads (cumulative)4,984
Downloads (12 Months)740
Downloads (6 Weeks)60
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14 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
October 2018 MEMSYS '18: Proceedings of the International Symposium on Memory Systems
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 3,   Downloads (12 Months): 40,   Downloads (Overall): 40

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Memory latency is a critical bottleneck in today's systems. The organization of the DRAM main memory necessitates sensing and reading an entire row (around 4KB) of data in order to access a single cache block. The benefit of this organization is that subsequent accesses to the same row can be ...

2 published by ACM
June 2018 DAC '18: Proceedings of the 55th Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 7,   Downloads (12 Months): 81,   Downloads (Overall): 173

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DRAM memory access is a critical performance bottleneck. To access one cache block, an entire row needs to be sensed and amplified, data restored into the bitcells and the bitlines precharged, incurring high latency. Isolating the bitlines and sense amplifiers after activation enables reads and precharges to happen in parallel. ...

3
June 2018 ISCA '18: Proceedings of the 45th Annual International Symposium on Computer Architecture
Publisher: IEEE Press
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 10,   Downloads (12 Months): 164,   Downloads (Overall): 164

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Increasing the capacity of the Last Level Cache (LLC) can help scale the memory wall. Due to prohibitive area and leakage power, however, growing conventional SRAM LLC already incurs diminishing returns. Emerging Non-Volatile Memory (NVM) technologies like Spin Torque Transfer RAM (STTRAM) promise high density and low leakage, thereby offering ...
Keywords: LLC, STTRAM, non-volatile

4
June 2018 ISCA '18: Proceedings of the 45th Annual International Symposium on Computer Architecture
Publisher: IEEE Press
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 14,   Downloads (12 Months): 127,   Downloads (Overall): 127

Full text available: PDFPDF
On-die caches are a popular method to help hide the main memory latency. However, it is difficult to build large caches without substantially increasing their access latency, which in turn hurts performance. To overcome this difficulty, on-die caches are typically built as a multi-level cache hierarchy. One such popular hierarchy ...
Keywords: caching, criticality, prefetching

5 published by ACM
November 2017 ACM Transactions on Architecture and Code Optimization (TACO): Volume 14 Issue 4, December 2017
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 12,   Downloads (12 Months): 131,   Downloads (Overall): 371

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Modern multi-core systems provide huge computational capabilities, which can be used to run multiple processes concurrently. To achieve the best possible performance within limited power budgets, the various system resources need to be allocated effectively. Any mismatch between runtime resource requirement and allocation leads to a sub-optimal energy-delay product (EDP). ...
Keywords: Energy efficient computation, and frequency scaling, cache management, computer architectures, dynamic voltage, low power architectures

6
March 2017 DATE '17: Proceedings of the Conference on Design, Automation & Test in Europe
Publisher: European Design and Automation Association
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 2,   Downloads (12 Months): 7,   Downloads (Overall): 18

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The widening gap between the processor and memory performance has led to the inclusion of multiple levels of caches in the modern multi-core systems. Processors with simultaneous multithreading (SMT) support multiple hardware threads on the same physical core, which results in shared private caches. Any inefficiency in the cache hierarchy ...

7 published by ACM
March 2017 ACM Transactions on Architecture and Code Optimization (TACO): Volume 14 Issue 1, April 2017
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 4,   Downloads (12 Months): 55,   Downloads (Overall): 192

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Recent research proposals on DRAM caches with conventional allocation units (64 or 128 bytes) as well as large allocation units (512 bytes to 4KB) have explored ways to minimize the space/latency impact of the tag store and maximize the effective utilization of the bandwidth. In this article, we study sectored ...
Keywords: DRAM cache, sectored cache, space utilization

8
June 2016 ISCA '16: Proceedings of the 43rd International Symposium on Computer Architecture
Publisher: IEEE Press
Bibliometrics:
Citation Count: 7
Downloads (6 Weeks): 3,   Downloads (12 Months): 33,   Downloads (Overall): 305

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The memory wall has motivated many enhancements to cache management policies aimed at reducing misses. Cache compression has been proposed to increase effective cache capacity, which potentially reduces capacity and conflict misses. However, complexity in cache compression implementations could increase cache power and access latency. On the other hand, advanced ...
Keywords: cache replacement policies, cache compression
Also published in:
October 2016  ACM SIGARCH Computer Architecture News - ISCA'16: Volume 44 Issue 3, June 2016

9
March 2016 DATE '16: Proceedings of the 2016 Conference on Design, Automation & Test in Europe
Publisher: EDA Consortium
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 0,   Downloads (12 Months): 7,   Downloads (Overall): 22

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Modern multicore architectures require runtime optimization techniques to address the problem of mismatches between the dynamic resource requirements of different processes and the runtime allocation. Choosing between multiple optimizations at runtime is complex due to the non-additive effects, making the adaptiveness of the machine learning techniques useful. We present a ...

10 published by ACM
December 2013 MICRO-46: Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: ACM
Bibliometrics:
Citation Count: 9
Downloads (6 Weeks): 1,   Downloads (12 Months): 13,   Downloads (Overall): 472

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Three-dimensional (3D) scene rendering is implemented in the form of a pipeline in graphics processing units (GPUs). In different stages of the pipeline, different types of data get accessed. These include, for instance, vertex, depth, stencil, render target (same as pixel color), and texture sampler data. The GPUs traditionally include ...
Keywords: 3D scene rendering, caches, graphics processing units

11 published by ACM
September 2012 PACT '12: Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Publisher: ACM
Bibliometrics:
Citation Count: 10
Downloads (6 Weeks): 1,   Downloads (12 Months): 23,   Downloads (Overall): 483

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The replacement policies for the last-level caches (LLCs) are usually designed based on the access information available locally at the LLC. These policies are inherently sub-optimal due to lack of information about the activities in the inner-levels of the hierarchy. This paper introduces cache hierarchy-aware replacement (CHAR) algorithms for inclusive ...
Keywords: last-level caches, replacement policy, bypass algorithm

12 published by ACM
June 2011 ISCA '11: Proceedings of the 38th annual international symposium on Computer architecture
Publisher: ACM
Bibliometrics:
Citation Count: 31
Downloads (6 Weeks): 2,   Downloads (12 Months): 42,   Downloads (Overall): 1,053

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Inclusive last-level caches (LLCs) waste precious silicon estate due to cross-level replication of cache blocks. As the industry moves toward cache hierarchies with larger inner levels, this wasted cache space leads to bigger performance losses compared to exclusive LLCs. However, exclusive LLCs make the design of replacement policies more challenging. ...
Keywords: bypass policy, exclusive last-level cache, insertion policy
Also published in:
June 2011  ACM SIGARCH Computer Architecture News - ISCA '11: Volume 39 Issue 3, June 2011

13 published by ACM
June 2004 PLDI '04: Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation
Publisher: ACM
Bibliometrics:
Citation Count: 28
Downloads (6 Weeks): 1,   Downloads (12 Months): 12,   Downloads (Overall): 1,147

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Cache miss stalls hurt performance because of the large gap between memory and processor speeds - for example, the popular server benchmark SPEC JBB2000 spends 45% of its cycles stalled waiting for memory requests on the Itanium® 2 processor. Traversing linked data structures causes a large portion of these stalls. ...
Keywords: cache misses, compiler optimization, garbage collection, prefetching, profile-guided optimization, virtual machines
Also published in:
June 2004  ACM SIGPLAN Notices - PLDI '04: Volume 39 Issue 6, May 2004

14 published by ACM
October 2000 ISMM '00: Proceedings of the 2nd international symposium on Memory management
Publisher: ACM
Bibliometrics:
Citation Count: 7
Downloads (6 Weeks): 0,   Downloads (12 Months): 5,   Downloads (Overall): 417

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The IA-64, Intel's 64-bit instruction set architecture, exhibits a number of interesting architectural features. Here we consider those features as they relate to supporting garbage collection (GC). We aim to assist GC and compiler implementors by describing how one may exploit features of the IA-64. Along the way, we record ...
Also published in:
January 2001  ACM SIGPLAN Notices: Volume 36 Issue 1, Jan 2001



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