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 Jesse G Beu

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Average citations per article2.43
Citation Count17
Publication count7
Publication years2005-2013
Available for download2
Average downloads per article751.50
Downloads (cumulative)1,503
Downloads (12 Months)27
Downloads (6 Weeks)2
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February 2013 HPCA '13: Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
Publisher: IEEE Computer Society
Citation Count: 2

As more heterogeneous architecture solutions continue to emerge, coherence solutions tailored for these architectures will become mandatory. Coherence hierarchies will likely continue to be prevalent in future large-scale shared memory architectures. However, past experience has shown that hierarchical coherence protocol design is a non-trivial problem, especially when considering the verification ...

November 2012 SCC '12: Proceedings of the 2012 SC Companion: High Performance Computing, Networking Storage and Analysis
Publisher: IEEE Computer Society
Citation Count: 1

A simulation system for modern multicore architectures is composed of various component models. For such a system to be useful for research purposes, modifiability is a key quality attribute. Users, when building a simulation model, need to have the capability to adjust various aspects of a component, or even replace ...
Keywords: parallel simulation, multicore, modifiable components, software design, software reuse

August 2012 MASCOTS '12: Proceedings of the 2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems
Publisher: IEEE Computer Society
Citation Count: 1

In the last decade, the microprocessor industry has undergone a dramatic change, ushering in the new era of multi-/manycore processors. As new designs incorporate increasing core counts, simulation technology has not matched pace, resulting in simulation times that increasingly dominate the design cycle. Complexities associated with the execution of code ...
Keywords: computer architecture, parallel architectures, multicore processing, simulation

August 2012 MASCOTS '12: Proceedings of the 2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems
Publisher: IEEE Computer Society
Citation Count: 1

Many new non-volatile memory technologies have been considered as a future scalable alternative to DRAM. Memory technologies such as MRAM, FeRAM, PCM have emerged as the most viable alternatives. But these memories have limited wear endurance. Practically realizable main memory systems employing these memory technologies are possible only if the ...
Keywords: PCM, Wear Leveling, Operating System

5 published by ACM
December 2011 MICRO-44: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: ACM
Citation Count: 3
Downloads (6 Weeks): 1,   Downloads (12 Months): 7,   Downloads (Overall): 219

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As technology continues to scale, the need for more sophisticated coherence management is becoming a necessity. The likely solution to this problem is the use of coherence hierarchies, analogous to how cache hierarchies have helped address the memory-wall problem in the past. Previous work in the construction of large-scale coherence ...
Keywords: cache coherence, memory hierarchies, multicore, manycore, coherence hierarchies

July 2011 IGCC '11: Proceedings of the 2011 International Green Computing Conference and Workshops
Publisher: IEEE Computer Society
Citation Count: 7

Phase Change Memory (PCM) has recently attracted a lot of attention as a scalable alternative to DRAM for main memory systems. As the need for high-density memory increases, DRAM has proven to be less attractive from the point of view of scaling and energy consumption. PCM-only memories suffer from latency ...
Keywords: DDR3 commodity DRAM memory system, energy efficient phase change memory, main memory, future high performance systems, energy consumption, latency issues, write energy, write endurance, cache, embedded DRAM

7 published by ACM
December 2005 ACM Transactions on Architecture and Code Optimization (TACO): Volume 2 Issue 4, December 2005
Publisher: ACM
Citation Count: 2
Downloads (6 Weeks): 1,   Downloads (12 Months): 20,   Downloads (Overall): 1,284

Full text available: PDFPDF
Effective data prefetching requires accurate mechanisms to predict embedded patterns in the miss reference behavior. This paper proposes a novel prefetching mechanism, called the spectral prefetcher (SP), that accurately identifies the pattern by dynamically adjusting to its frequency. The proposed mechanism divides the memory address space into tag concentration zones ...
Keywords: adaptive, autocorrelation, memory, frequency, L2 cache, Prefetch, absolute and differential domain

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