Andrew Putnam
Andrew Putnam

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anputnamatmicrosoft.com

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Bibliometrics: publication history
Average citations per article17.85
Citation Count357
Publication count20
Publication years2006-2017
Available for download15
Average downloads per article817.13
Downloads (cumulative)12,257
Downloads (12 Months)1,753
Downloads (6 Weeks)165
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22 results found Export Results: bibtexendnoteacmrefcsv

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1
April 2018 NSDI'18: Proceedings of the 15th USENIX Conference on Networked Systems Design and Implementation
Publisher: USENIX Association
Bibliometrics:
Citation Count: 0

Modern cloud architectures rely on each server running its own networking stack to implement policies such as tunneling for virtual networks, security, and load balancing. However, these networking stacks are becoming increasingly complex as features are added and as network speeds increase. Running these stacks on CPU cores takes away ...

2 published by ACM
October 2017 SOSP '17: Proceedings of the 26th Symposium on Operating Systems Principles
Publisher: ACM
Bibliometrics:
Citation Count: 24
Downloads (6 Weeks): 60,   Downloads (12 Months): 652,   Downloads (Overall): 2,396

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Performance of in-memory key-value store (KVS) continues to be of great importance as modern KVS goes beyond the traditional object-caching workload and becomes a key infrastructure to support distributed main-memory computation in data centers. Recent years have witnessed a rapid increase of network bandwidth in data centers, shifting the bottleneck ...
Keywords: Key-Value Store, Performance, Programmable Hardware

3 published by ACM
May 2017 CF'17: Proceedings of the Computing Frontiers Conference
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 11,   Downloads (Overall): 60

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Process technology improvements have historically allowed an effortless expansion of the capacity and capabilities of computers and the cloud with few changes to the underlying software or programming model. However, the end of Dennard Scaling means that performance and efficiency gains will rely on the customization of the hardware for ...

4 published by ACM
May 2017 GLSVLSI '17: Proceedings of the on Great Lakes Symposium on VLSI 2017
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 5,   Downloads (12 Months): 43,   Downloads (Overall): 182

Full text available: PDFPDF
The Catapult project has brought the power and performance of FPGA-based reconfigurable computing to Microsoft's hyperscale datacenters, accelerating major production cloud applications such as Bing web search and Microsoft Azure, and enabling a new generation of machine learning and artificial intelligence applications. Catapult is now deployed in nearly every new ...
Keywords: catapult, configurable cloud, smartnic

5 published by ACM
October 2016 Communications of the ACM: Volume 59 Issue 11, November 2016
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 8,   Downloads (12 Months): 125,   Downloads (Overall): 960

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Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost. It is challenging to improve all of these factors simultaneously. To advance datacenter capabilities beyond what commodity server designs can provide, we designed and built a composable, reconfigurable hardware fabric based on field programmable gate arrays (FPGA). Each ...

6
October 2016 MICRO-49: The 49th Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: IEEE Press
Bibliometrics:
Citation Count: 36
Downloads (6 Weeks): 30,   Downloads (12 Months): 208,   Downloads (Overall): 230

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Hyperscale datacenter providers have struggled to balance the growing need for specialized hardware (efficiency) with the economic benefits of homogeneity (manageability). In this paper we propose a new cloud architecture that uses reconfigurable logic to accelerate both network plane functions and applications. This Configurable Cloud architecture places a layer of ...

7 published by ACM
February 2016 FPGA '16: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 2,   Downloads (12 Months): 49,   Downloads (Overall): 315

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In 2015, a team of software and hardware developers at Microsoft shipped the world?s first commercial search engine accelerated using FPGAs in the datacenter. During the sprint to production, new algorithms in the Bing ranking service were ported into FPGAs and deployed to a production bed within several weeks of ...
Keywords: cloud computing, datacenters, fpgas, hardware-software co-design, reconfigurable computing

8
June 2014 ISCA '14: Proceeding of the 41st annual international symposium on Computer architecuture
Publisher: IEEE Press
Bibliometrics:
Citation Count: 183
Downloads (6 Weeks): 30,   Downloads (12 Months): 493,   Downloads (Overall): 1,665

Full text available: PDFPDF
Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost. It is challenging to improve all of these factors simultaneously. To advance datacenter capabilities beyond what commodity server designs can provide, we have designed and built a composable, reconfigurablefabric to accelerate portions of large-scale software services. Each instantiation ...
Also published in:
October 2014  ACM SIGARCH Computer Architecture News - ISCA '14: Volume 42 Issue 3, June 2014

9
May 2013 IEEE Micro: Volume 33 Issue 3, May 2013
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 0

The ability to safely keep a secret in memory is central to the vast majority of security schemes, but storing and erasing these secrets is a difficult problem in the face of an attacker who can obtain unrestricted physical access to the underlying hardware. Depending on the memory technology, the ...
Keywords: Computer architecture,Computer security,Memory management,Security,Hardware,physical inspection attacks,computer hardware,security,memory structures,computer architecture,cryptography

10
February 2013 HPCA '13: Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 3

Dynamic multicore architectures, that fuse and split cores at run time, potentially offer a level of performance/energy agility that static multicore designs cannot achieve. Conventional ISAs, however, have scalability limits to fusion. EDGE-based designs offer greater scalability but to date have been performance limited by significant microarchitectural bottlenecks. This paper ...

11
June 2012 ISCA '12: Proceedings of the 39th Annual International Symposium on Computer Architecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 5
Downloads (6 Weeks): 5,   Downloads (12 Months): 16,   Downloads (Overall): 306

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The ability to safely keep a secret in memory is central to the vast majority of security schemes, but storing and erasing these secrets is a difficult problem in the face of an attacker who can obtain unrestricted physical access to the underlying hardware. Depending on the memory technology, the ...
Also published in:
September 2012  ACM SIGARCH Computer Architecture News - ISCA '12: Volume 40 Issue 3, June 2012

12 published by ACM
January 2011 ACM SIGARCH Computer Architecture News: Volume 38 Issue 4, September 2010
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 6,   Downloads (12 Months): 17,   Downloads (Overall): 253

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Previous research has shown that Explicit Data Graph Execution (EDGE) instruction set architectures (ISA) allow for power efficient performance scaling. In this paper we describe the preliminary design of a new dynamic multicore processor called E2 that utilizes an EDGE ISA to allow for the dynamic composition of physical cores ...
Keywords: explicit data graph execution (EDGE)

13 published by ACM
November 2010 ACM Transactions on Reconfigurable Technology and Systems (TRETS): Volume 3 Issue 4, November 2010
Publisher: ACM
Bibliometrics:
Citation Count: 8
Downloads (6 Weeks): 3,   Downloads (12 Months): 19,   Downloads (Overall): 490

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High-Performance Reconfigurable Computers (HPRCs) consist of one or more standard microprocessors tightly-coupled with one or more reconfigurable FPGAs. HPRCs have been shown to provide good speedups and good cost/performance ratios, but not necessarily ease of use, leading to a slow acceptance of this technology. HPRCs introduce new design challenges, such ...
Keywords: Co-design, MPI, Parallel Programming, Programming Model, Reconfigurable, FPGA, High-Performance

14 published by ACM
June 2009 ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture
Publisher: ACM
Bibliometrics:
Citation Count: 6
Downloads (6 Weeks): 2,   Downloads (12 Months): 23,   Downloads (Overall): 1,436

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Many-cache is a memory architecture that efficiently supports caching in commercially available FPGAs. It facilitates FPGA programming for high-performance computing (HPC) developers by providing them with memory performance that is greater and power consumption that is less than their current CPU platforms, but without sacrificing their familiar, C-based programming environment. ...
Keywords: c-to-gates, c-to-hardware, caches, co-processor accelerator, fpga, many-cache, synthesis compiler
Also published in:
June 2009  ACM SIGARCH Computer Architecture News: Volume 37 Issue 3, June 2009

15 published by ACM
February 2009 FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 0

CHiMPS is a C-based compiler for high-performance computing (HPC) on heterogeneous CPU-FPGA computing platforms. CHiMPS efficiently supports random accesses to main memory through the many-cache memory model, enabling a broader range of applications to take advantage of FPGA-based acceleration. Many-cache creates multiple caches on top of an FGPA's small, independent ...
Keywords: c-to-gates, c-to-hardware, caches, co-processor accelerators, fpga

16
January 2009
Bibliometrics:
Citation Count: 0

Superscalar processors no longer scale as silicon process sizes shrink. Spatial dataflow computing architectures have emerged as a promising and scalable alternative to superscalars, but this promise depends on deliver better performance and power efficiency than superscalars, and on software developers adopting spatial dataflow architectures. My thesis research explores two ...

17 published by ACM
February 2008 FPGA '08: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 8

This poster describes CHiMPS, a toolflow that aims to provide software developers with a way to program hybrid CPU-FPGA platforms using familiar tools, languages, and techniques. CHiMPS starts with C and produces a specialized spatial dataflow architecture that supports coherent caches and the shared-memory programming model. The toolflow is designed ...
Keywords: FPGA, FPGA accelerators, c-to-gates, high-performance computing, reconfigurable computing

18 published by ACM
May 2007 ACM Transactions on Computer Systems (TOCS): Volume 25 Issue 2, May 2007
Publisher: ACM
Bibliometrics:
Citation Count: 22
Downloads (6 Weeks): 10,   Downloads (12 Months): 52,   Downloads (Overall): 1,643

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Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, however, is an open challenge that conventional superscalar designs will not be able to meet. We present WaveScalar as a scalable alternative to conventional designs. WaveScalar is a ...
Keywords: dataflow computing, WaveScalar, multithreading

19 published by ACM
October 2006 ASPLOS XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Publisher: ACM
Bibliometrics:
Citation Count: 14
Downloads (6 Weeks): 2,   Downloads (12 Months): 26,   Downloads (Overall): 940

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This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effectively minimizes operand latency. After this schedule has been partitioned into large sections, the bottom-level algorithm must more carefully analyze program structure when producing the ...
Keywords: dataflow, instruction scheduling, tiled architectures
Also published in:
October 2006  ACM SIGOPS Operating Systems Review - Proceedings of the 2006 ASPLOS Conference: Volume 40 Issue 5, December 2006 November 2006  ACM SIGPLAN Notices - Proceedings of the 2006 ASPLOS Conference: Volume 41 Issue 11, November 2006 October 2006  ACM SIGARCH Computer Architecture News - Proceedings of the 2006 ASPLOS Conference: Volume 34 Issue 5, December 2006

20 published by ACM
September 2006 PACT '06: Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 1,   Downloads (12 Months): 15,   Downloads (Overall): 406

Full text available: PDFPDF
In recent years, computer architects have proposed tiled architectures in response to several emerging problems in processor design, such as design complexity, wire delay, and fabrication reliability. One of these architectures, WaveScalar, uses a dynamic, tagged-token dataflow execution model to simplify the design of the processor tiles and their interconnection ...
Keywords: Wavescalar, compiler, tiled architecture, dataflow



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