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 Engin Ïpek

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Average citations per article39.66
Citation Count1,150
Publication count29
Publication years2005-2017
Available for download18
Average downloads per article1,029.89
Downloads (cumulative)18,538
Downloads (12 Months)1,912
Downloads (6 Weeks)166
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29 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
April 2017 ASPLOS '17: Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 14,   Downloads (12 Months): 218,   Downloads (Overall): 218

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Conventional off-chip voltage regulators are typically bulky and slow, and are inefficient at exploiting system and workload variability using Dynamic Voltage and Frequency Scaling (DVFS). On-die integration of voltage regulators has the potential to increase the energy efficiency of computer systems by enabling power control at a fine granularity in ...
Keywords: thermal management, computer architecture, energy, power
Also published in:
May 2017  ACM SIGPLAN Notices - ASPLOS '17: Volume 52 Issue 4, April 2017 May 2017  ACM SIGARCH Computer Architecture News - Asplos'17: Volume 45 Issue 1, March 2017

2 published by ACM
December 2015 MICRO-48: Proceedings of the 48th International Symposium on Microarchitecture
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 2,   Downloads (12 Months): 33,   Downloads (Overall): 167

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Data movement over long and highly capacitive interconnects is responsible for a large fraction of the energy consumed in nanometer ICs. DDRx, the most broadly adopted family of DRAM interfaces, contributes significantly to the overall system energy in a wide range of computer systems. To reduce the energy cost of ...
Keywords: energy-efficient design, memory interfaces, sparse representation

3
October 2015 ICCD '15: Proceedings of the 2015 33rd IEEE International Conference on Computer Design (ICCD)
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Near-threshold computing (NTC) is an effective technique for improving the energy efficiency of a CMOS microprocessor, but suffers from a significant performance loss and an increased sensitivity to voltage noise. MOS current-mode logic (MCML), a differential logic family, maintains a low voltage swing and a constant current, making it inherently ...

4
October 2015 ICCD '15: Proceedings of the 2015 33rd IEEE International Conference on Computer Design (ICCD)
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Data movement over long on-chip interconnects is a major contributor to system energy. This paper presents novel signaling and encoding techniques that toget her improve the energy efficiency of data communication between the processor cores and the last level cache. The proposed techniques make the interconnect energy proportional to the ...

5
February 2014 Microelectronics Journal: Volume 45 Issue 2, February, 2014
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 0

Novel spin torque transfer magnetic tunnel junction (STT-MTJ) based memory cell topologies are introduced to improve both the sense margin and the current ratio observed by the sense circuitry. These circuits utilize an additional transistor per cell in either a diode connected or gate connected manner and maintain leakage current ...
Keywords: Resistive memories, MRAM, VLSI

6 published by ACM
December 2013 ACM Transactions on Computer Systems (TOCS): Volume 31 Issue 4, December 2013
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 6,   Downloads (12 Months): 31,   Downloads (Overall): 339

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Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these controllers is to make them programmable—a proven technique that has seen wide ...
Keywords: Programmable, memory controller

7 published by ACM
December 2013 MICRO-46: Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 0,   Downloads (12 Months): 20,   Downloads (Overall): 261

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Increasing cache sizes in modern microprocessors require long wires to connect cache arrays to processor cores. As a result, the last-level cache (LLC) has become a major contributor to processor energy, necessitating techniques to increase the energy efficiency of data exchange over LLC interconnects. This paper presents an energy-efficient data ...
Keywords: caches, signaling, data encoding, interconnect, low power

8 published by ACM
June 2013 ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture
Publisher: ACM
Bibliometrics:
Citation Count: 16
Downloads (6 Weeks): 18,   Downloads (12 Months): 175,   Downloads (Overall): 696

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With technology scaling, on-chip power dissipation and off-chip memory bandwidth have become significant performance bottlenecks in virtually all computer systems, from mobile devices to supercomputers. An effective way of improving performance in the face of bandwidth and power limitations is to rely on associative memory systems. Recent work on a ...
Keywords: associative computing, STT-MRAM, TCAM
Also published in:
June 2013  ACM SIGARCH Computer Architecture News - ICSA '13: Volume 41 Issue 3, June 2013

9
May 2013 IEEE Micro: Volume 33 Issue 3, May 2013
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 0

Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these controllers is to make them programmable. Unfortunately, the stringent latency and throughput ...
Keywords: Computer architecture,Memory management,Computer programs,Programming,Computer interfaces,double data rate memory interface technology,programmability,memory controllers,DDRx,Pardis

10 published by ACM
June 2012 ICS '12: Proceedings of the 26th ACM international conference on Supercomputing
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 3,   Downloads (12 Months): 16,   Downloads (Overall): 216

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Though the prime target of multicore architectures is parallel and multithreaded workloads (which favors maximum core count ), executing sequential code fast continues to remain critical (which benefits from maximum core size ). This poses a difficult design trade-off. Core Fusion is a recently-proposed reconfigurable multicore architecture that attempts to ...
Keywords: genetic programming, instruction steering, multicore, core fusion, collective commit, microarchitecture, software diversity

11
June 2012 ISCA '12: Proceedings of the 39th Annual International Symposium on Computer Architecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 10
Downloads (6 Weeks): 1,   Downloads (12 Months): 18,   Downloads (Overall): 419

Full text available: PDFPDF
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these controllers is to make them programmable---a proven technique that has seen wide ...
Also published in:
September 2012  ACM SIGARCH Computer Architecture News - ISCA '12: Volume 40 Issue 3, June 2012

12 published by ACM
December 2011 MICRO-44: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: ACM
Bibliometrics:
Citation Count: 8
Downloads (6 Weeks): 5,   Downloads (12 Months): 98,   Downloads (Overall): 467

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Power dissipation and off-chip bandwidth restrictions are critical challenges that limit microprocessor performance. Ternary content addressable memories (TCAM) hold the potential to address both problems in the context of a wide range of data-intensive workloads that benefit from associative search capability. Power dissipation is reduced by eliminating instruction processing and ...
Keywords: resistive memory, accelerator, TCAM

13 published by ACM
July 2010 Communications of the ACM: Volume 53 Issue 7, July 2010
Publisher: ACM
Bibliometrics:
Citation Count: 19
Downloads (6 Weeks): 10,   Downloads (12 Months): 74,   Downloads (Overall): 1,148

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Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as dynamic random access memory (DRAM). In contrast, phase change memory (PCM) relies on programmable resistances, as well as scalable current and thermal mechanisms. To deploy PCM as a DRAM alternative ...

14 published by ACM
June 2010 ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture
Publisher: ACM
Bibliometrics:
Citation Count: 31
Downloads (6 Weeks): 5,   Downloads (12 Months): 117,   Downloads (Overall): 1,301

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As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold voltages in proportion to device dimensions, a practice that induces an exponential increase in subthreshold leakage. ...
Keywords: power-efficiency, STT-MRAM
Also published in:
June 2010  ACM SIGARCH Computer Architecture News - ISCA '10: Volume 38 Issue 3, June 2010

15 published by ACM
March 2010 ACM SIGARCH Computer Architecture News - ASPLOS '10: Volume 38 Issue 1, March 2010
Publisher: ACM
Bibliometrics:
Citation Count: 56
Downloads (6 Weeks): 4,   Downloads (12 Months): 80,   Downloads (Overall): 1,250

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DRAM is facing severe scalability challenges in sub-45nm tech- nology nodes due to precise charge placement and sensing hur- dles in deep-submicron geometries. Resistive memories, such as phase-change memory (PCM), already scale well beyond DRAM and are a promising DRAM replacement. Unfortunately, PCM is write-limited, and current approaches to managing ...
Keywords: phase-change memory, write endurance
Also published in:
March 2010  ACM SIGPLAN Notices - ASPLOS '10: Volume 45 Issue 3, March 2010 March 2010  ASPLOS XV: Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems

16
January 2010 IEEE Micro: Volume 30 Issue 1, January 2010
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 63

Phase-change memory may enable continued scaling of main memories, but PCM has higher access latencies, incurs higher power costs, and wears out more quickly than DRAM. This article discusses how to mitigate these limitations through buffer sizing, row caching, write reduction, and wear leveling, to make PCM a viable DRAM ...
Keywords: DRAM, energy efficiency, phase-change memory, PCM, memory architecture, phase-change memory, PCM, technology scaling, memory architecture, energy efficiency, DRAM, technology scaling

17 published by ACM
October 2009 SOSP '09: Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles
Publisher: ACM
Bibliometrics:
Citation Count: 188
Downloads (6 Weeks): 33,   Downloads (12 Months): 284,   Downloads (Overall): 1,873

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Modern computer systems have been built around the assumption that persistent storage is accessed via a slow, block-based interface. However, new byte-addressable, persistent memory technologies such as phase change memory (PCM) offer fast, fine-grained access to persistent storage. In this paper, we present a file system and a hardware architecture ...
Keywords: file systems, performance, phase change memory

18
September 2009 IEEE Micro: Volume 29 Issue 5, September 2009
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 14

A machine learning approach to multicore resource management produces self-optimizing on-chip hardware agents capable of learning, planning, and continuously adapting to changing workload demands. This results in more efficient and flexible management of critical hardware resources at runtime.
Keywords: machine learning., multicore, dynamic resource management, machine learning., dynamic resource management, multicore

19 published by ACM
June 2009 ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture
Publisher: ACM
Bibliometrics:
Citation Count: 324
Downloads (6 Weeks): 39,   Downloads (12 Months): 416,   Downloads (Overall): 4,471

Full text available: PDFPDF
Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM) storage relies on scalable current and thermal mechanisms. To exploit PCM's scalability as a DRAM alternative, PCM must be architected to address relatively ...
Keywords: dram alternative, power, scalability, pcm, phase change memory, endurance, performance, energy
Also published in:
June 2009  ACM SIGARCH Computer Architecture News: Volume 37 Issue 3, June 2009

20
November 2008 MICRO 41: Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 78
Downloads (6 Weeks): 6,   Downloads (12 Months): 92,   Downloads (Overall): 681

Full text available: PDFPDF
Efficient sharing of system resources is critical to obtaining high utilization and enforcing system-level performance objectives on chip multiprocessors (CMPs). Although several proposals that address the management of a single microarchitectural resource have been published in the literature, coordinated management of multiple interacting resources on CMPs remains an open problem.



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