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 Madhura Purnaprajna

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Bibliometrics: publication history
Average citations per article1.60
Citation Count16
Publication count10
Publication years2007-2015
Available for download5
Average downloads per article247.40
Downloads (cumulative)1,237
Downloads (12 Months)95
Downloads (6 Weeks)9
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10 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
February 2015 ACM Transactions on Embedded Computing Systems (TECS): Volume 14 Issue 2, March 2015
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 3,   Downloads (12 Months): 47,   Downloads (Overall): 229

Full text available: PDFPDF
The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementations often need to explore parameters, such as optimal bitwidth and data representation, through time-consuming Monte Carlo simulations. A ...
Keywords: Design space exploration, FPGAs, parallel computing, GPUs, OpenCL, simulation tools

2
April 2013 FCCM '13: Proceedings of the 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

Lookup table-based FPGAs offer flexibility but compromise on performance, as compared to custom CMOS implementations. This paper explores the idea of minimizing this performance gap by using fixed, fine-grained, nonprogrammable logic structures in place of lookup tables (LUTs). Functions previously mapped onto LUTs can now be diverted to these structures, ...
Keywords: Technology Mapping, FPGA architecture, Multiplexer

3 published by ACM
February 2013 FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 1

Despite their many advantages, FPGAs are still inefficient. This inefficiency is mainly due to programmable routing networks; however, FPGA logic blocks also have their share of contribution. From the performance perspective, fewer hops in the routing network translates to a shorter critical path; and that requires large logic blocks capable ...
Keywords: FPGA logic block, and-inverter cone, technology mapping, shadow logic

4
April 2012 FCCM '12: Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips need to explore parameters such as the optimal bit width and ...
Keywords: design space exploration, simulation tools, parallel computing, FPGAs, GPUs, LDPC decoding

5 published by ACM
January 2012 ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers: Volume 8 Issue 4, January 2012
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 2,   Downloads (12 Months): 25,   Downloads (Overall): 368

Full text available: PDFPDF
Soft and highly-customized processors are emerging as a common way to efficiently control large amount of computing resources available on FPGAs. Yet, some processor architectures of choice for DSP and media applications, such as wide-issue VLIW processors, remain impractical: the multi-ported register file makes a very inefficient use of the ...
Keywords: Soft-processor, resource efficiency, multi-port memory

6 published by ACM
September 2010 ACM Transactions on Reconfigurable Technology and Systems (TRETS): Volume 3 Issue 3, September 2010
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 3,   Downloads (12 Months): 14,   Downloads (Overall): 286

Full text available: PDFPDF
In multiprocessors, performance improvement is typically achieved by exploring parallelism with fixed granularities, such as instruction-level, task-level, or data-level parallelism. We introduce a new reconfiguration mechanism that facilitates variations in these granularities in order to optimize resource utilization in addition to performance improvements. Our reconfigurable multiprocessor QuadroCore combines the advantages ...
Keywords: compilation for multiprocessors, Reconfigurable multiprocessors

7
July 2009 AHS '09: Proceedings of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

A dynamically reconfigurable on-chip multiprocessor architecture is presented, which can be adapted to changing application demands and to faults detected at run-time. The scalable architecture comprises lightweight embedded RISC processors that are interconnected by a hierarchical network-on-chip (NoC). Reconfigurability is integrated into the processors as well as into the NoC ...

8 published by ACM
July 2009 ACM SIGARCH Computer Architecture News: Volume 37 Issue 2, May 2009
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 3,   Downloads (Overall): 223

Full text available: PDFPDF
To meet application-specific performance demands, architectures are predominantly redesigned and customised. Every architectural change results in huge overheads in design, verification, and fabrication, which together result in prolonged time-to-market. As an alternative, configurable architectures provide easy adaptability to different application domains in place of costly redesigns. To deal with application ...

9 published by ACM
March 2008 DATE '08: Proceedings of the conference on Design, automation and test in Europe
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 1,   Downloads (12 Months): 4,   Downloads (Overall): 126

Full text available: PDFPDF
Reconfigurable architectures are being increasingly used for their flexibility and extensive parallelism to achieve accelerations for computationally intensive applications. Although these architectures provide easy adaptability, it is so with an overhead in terms of area, power and timing, as compared to non-reconfigurable ASICs. Here, we propose a low overhead reconfigurable ...

10
July 2007 Journal of Systems Architecture: the EUROMICRO Journal: Volume 53 Issue 7, July, 2007
Publisher: Elsevier North-Holland, Inc.
Bibliometrics:
Citation Count: 7

A scheme for time and power efficient embedded system design, using hardware and software components, is presented. Our objective is to reduce the execution time and the power consumed by the system, leading to the simultaneous multi-objective minimization of time and power. The goal of suitably partitioning the system into ...
Keywords: Hardware-software partitioning, Reconfiguration, Genetic algorithms



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