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 Chad Leland Mitchell

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Average citations per article9.50
Citation Count38
Publication count4
Publication years1986-1990
Available for download1
Average downloads per article537.00
Downloads (cumulative)537
Downloads (12 Months)13
Downloads (6 Weeks)2
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1 published by ACM
August 1990 ACM Transactions on Computer Systems (TOCS): Volume 8 Issue 3, Aug. 1990
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 2,   Downloads (12 Months): 13,   Downloads (Overall): 537

Full text available: PDFPDF
The relative amount of instruction traffic for two architectures is about the same in the presence of a large cache as with no cache. Furthermore, the presence of an intermediate-sized cache probably substantially favors the denser architecture. Encoding techniques have a much greater impact on instruction traffic than do the ...

2
January 1988 IEEE Design & Test: Volume 5 Issue 1, January 1988
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 13

The authors present a high-level simulator that supports a top-down architectural analysis of embedded, custom applications. This tool characterizes more than 50 instruction-set variants and allows data such as instruction cached performance, data cache performance, register set size, and register allocation policy to be evaluated for all the architectures simultaneously. ...

3
September 1987 Computer: Volume 20 Issue 9, September 1987
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 19

First Page of the Article

4
June 1986
Bibliometrics:
Citation Count: 3

Previously, analysis of processor architecture has involved the measurement of hardware or interpreters. The use of benchmarks written in high-level languages has added the requirement for the compiler targeted to each architecture studied. Herein, a methodology based on the use of compiler tools has been developed which allows simulation of ...



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