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 Simone Campanoni

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Average citations per article4.76
Citation Count100
Publication count21
Publication years2008-2017
Available for download13
Average downloads per article255.31
Downloads (cumulative)3,319
Downloads (12 Months)656
Downloads (6 Weeks)120
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21 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
November 2017 Communications of the ACM: Volume 60 Issue 12, December 2017
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 97,   Downloads (12 Months): 334,   Downloads (Overall): 334

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Because of the high cost of communication between processors, compilers that parallelize loops automatically have been forced to skip a large class of loops that are both critical to performance and rich in latent parallelism. HELIX-RC is a compiler/microprocessor co-design that opens those loops to parallelization by decoupling communication from ...

2 published by ACM
March 2016 CC 2016: Proceedings of the 25th International Conference on Compiler Construction
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 5,   Downloads (12 Months): 59,   Downloads (Overall): 161

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Recent approaches to automatic parallelization have taken advantage of the low-latency on-chip interconnect provided in modern multicore processors, demonstrating significant speedups, even for complex workloads. Although these techniques can already extract significant thread-level parallelism from application loops, we are interested in quantifying and exploiting any additional performance that remains on ...
Keywords: Transactional Memory, Thread-Level Speculation

3
October 2015 CODES '15: Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis
Publisher: IEEE Press
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 5,   Downloads (Overall): 57

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Resources such as quantities of transistors and memory, the level of integration and the speed of components have increased dramatically over the years. Even though the technologies have improved, we continue to apply outdated approaches to our use of these resources. Key computer science abstractions have not changed since the ...

4
February 2015 CGO '15: Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 4,   Downloads (12 Months): 48,   Downloads (Overall): 152

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Automatic generation of parallel code for general-purpose commodity processors is a challenging computational problem. Nevertheless, there is a lot of latent thread-level parallelism in the way sequential programs are actually used. To convert latent parallelism into performance gains, users may be willing to compromise on the quality of a program's ...

5
June 2014 ISCA '14: Proceeding of the 41st annual international symposium on Computer architecuture
Publisher: IEEE Press
Bibliometrics:
Citation Count: 10
Downloads (6 Weeks): 3,   Downloads (12 Months): 61,   Downloads (Overall): 394

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Data dependences in sequential programs limit parallelization because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual dependences counteract the benefits of parallelization. To address these challenges, we propose a lightweight architectural enhancement co-designed with a parallelizing ...
Also published in:
October 2014  ACM SIGARCH Computer Architecture News - ISCA '14: Volume 42 Issue 3, June 2014

6
July 2012 IEEE Micro: Volume 32 Issue 4, July 2012
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 4

Improving system performance increasingly depends on exploiting microprocessor parallelism, yet mainstream compilers still don't parallelize code automatically. Helix automatically parallelizes general-purpose programs without requiring any special hardware; avoids slowing down compiled programs, making it a suitable candidate for mainstream compilers; and outperforms the most similar historical technique that has been ...
Keywords: Prefetching,Parallel processing,Synchronization,Encoding,Optimization,robustness of code optimization,Prefetching,Parallel processing,Synchronization,Encoding,Optimization,DOACROSS parallelism,extraction of coarse-grained parallelism

7 published by ACM
June 2012 DAC '12: Proceedings of the 49th Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 13,   Downloads (Overall): 245

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Parallelism has become the primary way to maximize processor performance and power efficiency. But because creating parallel programs by hand is difficult and prone to error, there is an urgent need for automatic ways of transforming conventional programs to exploit modern multicore systems. The HELIX compiler transformation is one such ...
Keywords: coarse grain parallelism extraction, multiple programs, runtime code adaptability

8 published by ACM
June 2012 DAC '12: Proceedings of the 49th Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 13
Downloads (6 Weeks): 4,   Downloads (12 Months): 26,   Downloads (Overall): 260

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In this paper, we present Metronome: a framework to enhance commodity operating systems with self-adaptive capabilities. The Metronome framework features two distinct components: Heart Rate Monitor (HRM) and Performance--Aware Fair Scheduler (PAFS). HRM is an active monitoring infrastructure implementing the observe phase of a self--adaptive computing system Observe--Decide--Act (ODA) control ...
Keywords: performance management, self-adaptive computing, operating systems

9 published by ACM
March 2012 CGO '12: Proceedings of the Tenth International Symposium on Code Generation and Optimization
Publisher: ACM
Bibliometrics:
Citation Count: 20
Downloads (6 Weeks): 2,   Downloads (12 Months): 70,   Downloads (Overall): 487

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We describe and evaluate HELIX, a new technique for automatic loop parallelization that assigns successive iterations of a loop to separate threads. We show that the inter-thread communication costs forced by loop-carried data dependences can be mitigated by code optimization, by using an effective heuristic for selecting loops to parallelize, ...

10
September 2011
Bibliometrics:
Citation Count: 0

This book is a guide to getting started with ILDJIT, a compilation framework designed to be both easily extensible and easily configurable. Within this framework, it is possible to build a tool-chain by customizing ILDJIT for specific purposes. Customizations can be used within both static and dynamic compilers already included ...

11
March 2011 CHANGE '11: Proceedings of the 2011 1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Object-code virtualization, commonly used to achieve software portability, relies on a virtual execution environment, typically comprising an interpreter used for initial execution of methods, and a JIT for native code generation. The availability of multiple processors on current architectures makes it attractive to perform dynamic compilation in parallel with application ...

12
January 2011 IEEE Micro: Volume 31 Issue 1, January 2011
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 4

Voltage variations are a major challenge in processor design. Here, researchers characterize the voltage noise characteristics of programs as they run to completion on a production Core 2 Duo processor. Furthermore, they characterize the implications of resilient architecture design for voltage variation in future systems.
Keywords: processor design, Software thread scheduling, Software thread scheduling, processor design, dI/dt, voltage margins, inductive noise, dI/dt, inductive noise, voltage margins

13
December 2010 MICRO '43: Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 12
Downloads (6 Weeks): 0,   Downloads (12 Months): 5,   Downloads (Overall): 226

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Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die voltage as the processor runs single-threaded, multi-threaded, and multi-program workloads, we determine the average ...
Keywords: dI/dt, inductive noise, error resiliency, voltage droop, hw/sw co-design, thread scheduling, hardware reliability

14 published by ACM
October 2010 ACM Transactions on Architecture and Code Optimization (TACO): Volume 7 Issue 2, September 2010
Publisher: ACM
Bibliometrics:
Citation Count: 6
Downloads (6 Weeks): 3,   Downloads (12 Months): 11,   Downloads (Overall): 240

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In recent years, circuit reliability in modern high-performance processors has become increasingly important. Shrinking feature sizes and diminishing supply voltages have made circuits more sensitive to microprocessor supply voltage fluctuations. These fluctuations result from the natural variation of processor activity as workloads execute, but when left unattended, these voltage fluctuations ...
Keywords: dI/dt, inductive noise, Voltage noise, voltage emergencies

15
February 2010 Software—Practice & Experience: Volume 40 Issue 2, February 2010
Publisher: John Wiley & Sons, Inc.
Bibliometrics:
Citation Count: 8

ILDJIT, a new-generation dynamic compiler and virtual machine designed to support parallel compilation, is introduced here. Our dynamic compiler targets the increasingly popular ECMA-335 specification. The goal of this project is twofold: on one hand, it aims at exploiting the parallelism exposed by multi-core architectures to hide the dynamic compilation ...
Keywords: CIL dynamic compiler, dynamic adaptation, parallel virtual machine

16 published by ACM
July 2009 DAC '09: Proceedings of the 46th Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 1,   Downloads (12 Months): 8,   Downloads (Overall): 129

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Power constrained designs are becoming increasingly sensitive to supply voltage noise. We propose a hardware-software collaborative approach to enable aggressive operating margins: a checkpoint-recovery mechanism corrects margin violations, while a run-time software layer reschedules the program's instruction stream to prevent recurring margin crossings at the same program location. The run-time ...
Keywords: hardware software co-design, runtime optimization

17 published by ACM
July 2009 ICOOOLPS '09: Proceedings of the 4th workshop on the Implementation, Compilation, Optimization of Object-Oriented Languages and Programming Systems
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 0,   Downloads (12 Months): 18,   Downloads (Overall): 344

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This paper presents a Just-In-Time compilation system for ARM processors. The complete architecture is described, starting from static compilation of the sources into CIL (Common Intermediate Language) bytecode. The intermediate languages that are used are explained, together with the instuction selection and code generation techiniques. Finally, some experimental results are ...
Keywords: dynamic compilation, embedded systems, ARM

18
July 2009 DLT '09: Proceedings of the 13th International Conference on Developments in Language Theory
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 0

This is a new applied development of trace theory to compilation. Trace theory allows to commute independent program instructions, but overlooks the differences between control and data dependencies. Control(C)-dependences, unlike data-dependences, are determined by the Control Flow Graph, modelled as a local DFA. To ensure semantic equivalence, partial commutation must ...

19
March 2009 CC '09: Proceedings of the 18th International Conference on Compiler Construction: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 5

Object-code virtualization, commonly used to achieve software portability, relies on a virtual execution environment, typically comprising an interpreter used for initial execution of methods, and a JIT for native code generation. The availability of multiple processors on current architectures makes it attractive to perform dynamic compilation in parallel with application ...

20
September 2008 DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

System-level design of WSNs includes the selection of the sensing nodes and their dissemination in the environment to be monitored. Many design choices have to be taken during this stage of the development of the application. The goal of this paper is to present a methodology to specify formally the ...
Keywords: Wireless sensor networks, sensitivity analyis, system-level design, modeling, board level optimization



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