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 Yongjoo Kim

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Average citations per article6.33
Citation Count57
Publication count9
Publication years2008-2016
Available for download5
Average downloads per article436.20
Downloads (cumulative)2,181
Downloads (12 Months)125
Downloads (6 Weeks)14
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9 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
January 2016 ACM Transactions on Embedded Computing Systems (TECS): Volume 15 Issue 1, February 2016
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 5,   Downloads (12 Months): 48,   Downloads (Overall): 203

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Coarse-Grained Reconfigurable Architectures (CGRAs) are drawing significant attention since they promise both performances with parallelism and flexibility with reconfiguration. Soft errors (or transient faults) are becoming a serious design concern in embedded systems including CGRAs since the soft error rate is increasing exponentially as technology is scaling. A recently proposed ...
Keywords: TMR, reconfigurable architecture, selective validation, CGRA, DMR, soft error

2
March 2012 ARC'12: Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 1

Reconfigurable Architecture (RA), which provides extremely high energy efficiency for certain domains of applications, have one problem that current mapping algorithms for it do not scale well with the number of cores. One approach to this problem is using SIMD (Single Instruction Multiple Data) paradigm. However, SIMD can complicate the ...
Keywords: memory bank conflict, sequential, interleaving, application mapping, coarse-grained reconfigurable architecture

3 published by ACM
January 2012 ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers: Volume 8 Issue 4, January 2012
Publisher: ACM
Bibliometrics:
Citation Count: 13
Downloads (6 Weeks): 4,   Downloads (12 Months): 32,   Downloads (Overall): 599

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Pipelining algorithms are typically concerned with improving only the steady-state performance, or the kernel time. The pipeline setup time happens only once and therefore can be negligible compared to the kernel time. However, for Coarse-Grained Reconfigurable Architectures (CGRAs) used as a coprocessor to a main processor, pipeline setup can take ...
Keywords: compilation, nested loop, software pipelining, Coarse-grained reconfigurable architecture

4
November 2011 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Volume 30 Issue 11, November 2011
Publisher: IEEE Press
Bibliometrics:
Citation Count: 7

Coarse-grained reconfigurable arrays (CGRAs) are a very promising platform, providing both up to 10–100 MOps/mW of power efficiency and software programmability. However, this promise of CGRAs critically hinges on the effectiveness of application mapping onto CGRA platforms. While previous solutions have greatly improved the computation speed, they have largely ignored ...

5 published by ACM
October 2011 ACM Transactions on Design Automation of Electronic Systems (TODAES): Volume 16 Issue 4, October 2011
Publisher: ACM
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 1,   Downloads (12 Months): 21,   Downloads (Overall): 428

Full text available: PDFPDF
Coarse-grained reconfigurable architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and moving the complexity to application mapping. One major challenge comes in the form of data mapping. For reasons of power-efficiency and complexity, CGRAs use multibank local memory, and ...
Keywords: Coarse-grained reconfigurable architecture, Compilation, multibank memory, bank conflict, array mapping

6 published by ACM
April 2010 LCTES '10: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Publisher: ACM
Bibliometrics:
Citation Count: 9
Downloads (6 Weeks): 3,   Downloads (12 Months): 19,   Downloads (Overall): 369

Full text available: PDFPDF
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and moving the complexity to application mapping. One major challenge comes in the form of data mapping. For reasons of power-efficiency and complexity, CGRAs use multi-bank local memory, ...
Keywords: arbiter, bank conflict, compilation, coarse-grained reconfigurable architecture, multi-bank memory
Also published in:
April 2010  ACM SIGPLAN Notices - LCTES '10: Volume 45 Issue 4, April 2010

7
January 2010 HiPEAC'10: Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 4

Coarse-Grained Reconfigurable Arrays (CGRAs) are a very promising platform, providing both, up to 10-100 MOps/mW of power efficiency and are software programmable. However, this cardinal promise of CGRAs critically hinges on the effectiveness of application mapping onto CGRA platforms. While previous solutions have greatly improved the computation speed, they have ...

8
June 2009 HPCC '09: Proceedings of the 2009 11th IEEE International Conference on High Performance Computing and Communications
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

Although 32-bit architectures are becoming the norm for modern microprocessors, 16-bit ones are still employed by many low-end processors, for which small size and low power consumption are of high priority. However, 16-bit architectures have a critical disadvantage for embedded processors that they do not provide enough encoding space to ...
Keywords: embedded processor, addressing mode

9 published by ACM
July 2008 ACM Transactions on Design Automation of Electronic Systems (TODAES): Volume 13 Issue 3, July 2008
Publisher: ACM
Bibliometrics:
Citation Count: 18
Downloads (6 Weeks): 1,   Downloads (12 Months): 5,   Downloads (Overall): 582

Full text available: PDFPDF
As more processing elements are integrated in a single chip, embedded software design becomes more challenging: It becomes a parallel programming for nontrivial heterogeneous multiprocessors with diverse communication architectures, and design constraints such as hardware cost, power, and timeliness. In the current practice of parallel programming with MPI or OpenMP, ...
Keywords: design-space exploration, parallel-programming, Embedded software, software generation, multiprocessor system on chip



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