Author image not provided
 Chris Rowen

Authors:
Add personal information
  Affiliation history
Bibliometrics: publication history
Average citations per article4.56
Citation Count114
Publication count25
Publication years1982-2016
Available for download13
Average downloads per article428.08
Downloads (cumulative)5,565
Downloads (12 Months)131
Downloads (6 Weeks)18
SEARCH
ROLE


SUBJECT AREAS
See all subject areas



BOOKMARK & SHARE


25 results found Export Results: bibtexendnoteacmrefcsv

Result 1 – 20 of 25
Result page: 1 2

Sort by:

1
July 2016 IEEE Micro: Volume 36 Issue 4, July 2016
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 0

This column features retrospectives from the authors of six MICRO Test of Time award-winning papers: "MIPS: A Microprocessor Architecture" by Norman Jouppi and colleagues; "HPS, A New Microarchitecture: Rationale and Introduction" by Yale Patt, Wen-Mei Hwu, and Mike Shebanow; "Critical Issues Regarding HPS, A High Performance Microarchitecture" by Yale Patt ...

2
March 2010 DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe
Publisher: European Design and Automation Association
Bibliometrics:
Citation Count: 0

With the majority of chip real estate being filled with re-used IP blocks, the process of block assembly has significantly grown in importance. Marketing literature seems to suggest that assembling a chip from IP is as easy as browsing a library of blocks, assembling them in a block diagram and ...

3
November 2009 Computer: Volume 42 Issue 11, November 2009
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 18

A many-core processor design for high-performance systems draws from embedded computing's low-power architectures and design processes, providing a radical alternative to cluster solutions.
Keywords: Application-driven design, Embedded systems, Green Flash, Chip architectures, Climate modeling, Extreme-scale computing, Extreme-scale computing, Chip architectures, Green Flash, Application-driven design, Climate modeling, Embedded systems

4
October 2009 SOC'09: Proceedings of the 11th international conference on System-on-chip
Publisher: IEEE Press
Bibliometrics:
Citation Count: 4

The high computation demands of next generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. This paper introduces a new DSP architecture optimized for baseband applications, especially applications with heavy workload of complex filtering, FFT and MIMO matrix operations such as LTE. The Tensilica ...

5 published by ACM
June 2008 DAC '08: Proceedings of the 45th annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 4,   Downloads (Overall): 95

Full text available: PDFPDF
The DAC community will have an opportunity to offer its perspective and thoughts on the political landscape in the United States. With election season in full swing, the country is about to elect a new administration that could be from a new party.

6
January 2007 ASP-DAC '07: Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 1,   Downloads (12 Months): 2,   Downloads (Overall): 144

Full text available: PDFPDF
Next-generation embedded systems in application domains such as multimedia, wired and wireless communications, and multipurpose portable devices, are increasingly turning to multiprocessor platforms as a vehicle for their realization. But entirely fixed platforms composed of entirely fixed components lack the flexibility and ability to be optimized to the application to ...

7
January 2007 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Next-generation embedded systems in application domains such as multimedia, wired and wireless communications, and multipurpose portable devices, are increasingly turning to multiprocessor platforms as a vehicle for their realization. But entirely fixed platforms composed of entirely fixed components lack the flexibility and ability to be optimized to the application to ...

8 published by ACM
September 2005 CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 2,   Downloads (12 Months): 6,   Downloads (Overall): 238

Full text available: PDFPDF
Among the many directions of IT, the most pervasive is the fusion of information processing with physical processes - called embedded computing. It is the basic engine of innovation and source of competitiveness for broad range of industrial sectors from automotive to telecommunications and from aerospace to manufacturing. Embedded computing ...
Keywords: behavioral synthesis, binding, concurrent systems, scheduling, system level design, systems-on-chip

9 published by ACM
September 2005 EMSOFT '05: Proceedings of the 5th ACM international conference on Embedded software
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 2,   Downloads (12 Months): 4,   Downloads (Overall): 251

Full text available: PDFPDF
Among the many directions of IT, the most pervasive is the fusion of information processing with physical processes -- called embedded computing. It is the basic engine of innovation and source of competitiveness for broad range of industrial sectors from automotive to telecommunications and from aerospace to manufacturing. Embedded computing ...

10 published by ACM
June 2005 DAC '05: Proceedings of the 42nd annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 0,   Downloads (12 Months): 8,   Downloads (Overall): 394

Full text available: PDFPDF
Configurable processors enable dramatic gains in energy efficiency, relative to traditional fixed instruction-set processors. This energy advantage comes from three improvements. First, configuration of the instruction set permits a much closer fit of the processor to the target applications, reducing the number of execution cycles required. Second, configuring the processor ...
Keywords: PVT (process, voltage, temperature), dynamic power, SOC (system on chip), dynamic power efficiency, configurable embedded processor, leakage power, low-power, scaled VDD

11 published by ACM
June 2004 DAC '04: Proceedings of the 41st annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 5
Downloads (6 Weeks): 0,   Downloads (12 Months): 4,   Downloads (Overall): 410

Full text available: PDFPDF
This paper focuses on a particular SOC design technology and methodology, here called the advanced or processor-centric SOC design method, which reduces the risk of SOC design and increases ROI by using configurable processors to implement on-chip functions while increasing the SOC's flexibility through software programmability. The essential enabler for ...
Keywords: RISC, processor cores, RTL, MPSOC, SOC

12 published by ACM
June 2004 DAC '04: Proceedings of the 41st annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 2,   Downloads (12 Months): 2,   Downloads (Overall): 248

Full text available: PDFPDF
Increasing design cost and risk is causing more and more designers to build configurable platforms that will amortize design and manufacturing costs across many generations. Several reconfiguration schemes exist and none of them seems to be a clear winner. Most notably there are three forms of technology: structured ASIC, configurable ...

13
March 2003 DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 6,   Downloads (12 Months): 10,   Downloads (Overall): 45

Full text available: PDFPDF

14
December 2002 Computer: Volume 35 Issue 12, December 2002
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 3

To remain competitive, system-on-chip designers must keep pace with silicon technology's rapid evolution.One approach to speeding development of megagate SoCs uses multiple micro-processor cores to perform much of the processing currently relegated to register-transfer-level (RTL) techniques. Although general-purpose embedded processors handle many tasks, they often lack the bandwidth needed to ...

15 published by ACM
June 2001 DAC '01: Proceedings of the 38th annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 29
Downloads (6 Weeks): 1,   Downloads (12 Months): 9,   Downloads (Overall): 567

Full text available: PDFPDF
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned logic solutions with the flexibility of standard high-level programming methodology. Automated extension of processor function units and the associated software environment - compilers, debuggers, simulators and real-time operating systems - satisfies these ...

16 published by ACM
June 2000 DAC '00: Proceedings of the 37th Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 0

Advances in device technology have led to an era where entire systems can be implemented on a single component, commonly referred to as system-on-chip. With shrinking product life cycles placing severe time to market demands on manufacturers, coupled with their need to quickly change a product's feature set to address ...

17
October 1999 IEEE Design & Test: Volume 16 Issue 4, October 1999
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 2

First Page of the Article

18 published by ACM
June 1999 DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 0,   Downloads (12 Months): 2,   Downloads (Overall): 196

Full text available: PDFPDF

19 published by ACM
August 1988 ACM Transactions on Computer Systems (TOCS): Volume 6 Issue 3, Aug. 1988
Publisher: ACM
Bibliometrics:
Citation Count: 9
Downloads (6 Weeks): 6,   Downloads (12 Months): 22,   Downloads (Overall): 1,215

Full text available: PDFPDF
MIPS is a 32-bit processor architecture that has been implemented as an nMOS VLSI chip. The instruction set architecture is RISC-based. Close coupling with compilers and efficient use of the instruction set by compiled programs were goals of the architecture. The MIPS architecture requires that the software implement some constraints ...

20
May 1988 IEEE Micro: Volume 8 Issue 3, May 1988
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 4

A description is given of the R3010 floating-point accelerator chip, a coprocessor that is based on advanced reduced-instruction-set-computer (RISC) architecture and VLSI design techniques and provides high-speed floating-point operation. The 75000-transistor hard-wired chip executes four instructions in parallel. Its performance is compared with that of available floating-point processors and its ...



The ACM Digital Library is published by the Association for Computing Machinery. Copyright © 2018 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us