Author image not provided
 Jinho Suh

Authors:
Add personal information
  Affiliation history
Bibliometrics: publication history
Average citations per article4.67
Citation Count28
Publication count6
Publication years2009-2015
Available for download4
Average downloads per article305.00
Downloads (cumulative)1,220
Downloads (12 Months)56
Downloads (6 Weeks)4
SEARCH
ROLE
Arrow RightAuthor only


AUTHOR'S COLLEAGUES
See all colleagues of this author

SUBJECT AREAS
See all subject areas




BOOKMARK & SHARE


6 results found Export Results: bibtexendnoteacmrefcsv

Result 1 – 6 of 6
Sort by:

1 published by ACM
April 2015 ACM Transactions on Architecture and Code Optimization (TACO): Volume 12 Issue 1, April 2015
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 2,   Downloads (12 Months): 18,   Downloads (Overall): 138

Full text available: PDFPDF
Modern microprocessor cores reach their high performance levels with the help of high clock rates, parallel and speculative execution of a large number of instructions, and vast cache hierarchies. Modern cores also have adaptive features to regulate power and temperature and avoid thermal emergencies. All of these features contribute to ...
Keywords: EPI, Power, energy

2
June 2013 DSN '13: Proceedings of the 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

In this paper, we introduce PHYS (Profiled-HYbrid Sampling), a sampling framework for soft-error benchmarking of caches. Reliability simulations of caches are much more complex than performance simulations and therefore exhibit large simulation slowdowns (two orders of magnitude) over performance simulations. The major problem is that the reliability lifetime of every ...
Keywords: Reliability,Benchmark testing,Analytical models,Sociology,Statistics,Acceleration,Target tracking,simulation sampling,Soft-error,reliability benchmarking

3
February 2012 HPCA '12: Proceedings of the 2012 IEEE 18th International Symposium on High-Performance Computer Architecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 6

Due to the growing trend that a Single Event Upset (SEU) can cause spatial Multi-Bit Upsets (MBUs), the effects of spatial MBUs has recently become an important yet very challenging issue, especially in large, last-level caches (LLCs) protected by protection codes. In the presence of spatial MBUs, the strength of ...

4 published by ACM
June 2011 SIGMETRICS '11: Proceedings of the ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Publisher: ACM
Bibliometrics:
Citation Count: 7
Downloads (6 Weeks): 1,   Downloads (12 Months): 10,   Downloads (Overall): 275

Full text available: PDFPDF
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches due to soft errors is critical to evaluate the relative merits of a plethora of protection schemes that are being proposed to ...
Keywords: cache, reliability, soft error

5 published by ACM
June 2011 ACM SIGMETRICS Performance Evaluation Review - Performance evaluation review: Volume 39 Issue 1, June 2011
Publisher: ACM
Bibliometrics:
Citation Count: 5
Downloads (6 Weeks): 1,   Downloads (12 Months): 15,   Downloads (Overall): 156

Full text available: PDFPDF
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches due to soft errors is critical to evaluate the relative merits of a plethora of protection schemes that are being proposed to ...
Keywords: cache, reliability, soft error

6 published by ACM
June 2009 ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture
Publisher: ACM
Bibliometrics:
Citation Count: 7
Downloads (6 Weeks): 0,   Downloads (12 Months): 13,   Downloads (Overall): 651

Full text available: PDFPDF
Today's microprocessor cores reach high performance levels not only by their high clock rate but also by the concurrent execution of a large number of instructions. Because of the relationship between power and frequency, it becomes attractive to run an OoO (Out-of-Order) core at a frequency lower than its nominal ...
Keywords: embedded systems, ooo processors, real-time systems, stabilization, variability
Also published in:
June 2009  ACM SIGARCH Computer Architecture News: Volume 37 Issue 3, June 2009



The ACM Digital Library is published by the Association for Computing Machinery. Copyright © 2018 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us