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 Xiaohang Wang

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Average citations per article3.13
Citation Count25
Publication count8
Publication years2009-2013
Available for download1
Average downloads per article555.00
Downloads (cumulative)555
Downloads (12 Months)18
Downloads (6 Weeks)1
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8 results found Export Results: bibtexendnoteacmrefcsv

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1
October 2013 Journal of Systems Architecture: the EUROMICRO Journal: Volume 59 Issue 9, October, 2013
Publisher: Elsevier North-Holland, Inc.
Bibliometrics:
Citation Count: 0

3-D Networks-on-Chip (NoCs) have been proposed as a potent solution to address both the interconnection and design complexity problems facing future System-on-Chip (SoC) designs. In this paper, two topology-aware multicast routing algorithms, Multicasting XYZ (MXYZ) and Alternative XYZ (AL+XYZ) algorithms in supporting of 3-D NoC are proposed. In essence, MXYZ ...
Keywords: Multicast, Networks-on-Chip (NoCs), Routing algorithms

2
October 2011 NPC'11: Proceedings of the 8th IFIP international conference on Network and parallel computing
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 1

3-D Networks-on-Chip (NoCs) emerge as a powerful solution to address both the interconnection and design complexity problems facing future Systems-on-Chip (SoCs). Effective run-time application mapping on a 3-D NoC-based Multiprocessor Systems-on-Chip (MPSoC) can be quite challenging, largely due to the fact that the arrival order and task graphs of the ...
Keywords: application mapping, 3-D IC, networks-on-chip

3
March 2011 Microprocessors & Microsystems: Volume 35 Issue 2, March, 2011
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 7

When a number of applications simultaneously running on a many-core chip multiprocessor (CMP) chip connected through network-on-chip (NoC), significant amount of on-chip traffic is one-to-many (multicast) in nature. As a matter of fact, when multiple applications are mapped onto an NoC architecture with applicable traffic isolation constraints, the corresponding sub-networks ...
Keywords: Network-on-chips (NoCs), Chip multiprocessor (CMP), Multicast, Routing

4
January 2011 International Journal of High Performance Systems Architecture: Volume 3 Issue 1, January 2011
Publisher: Inderscience Publishers
Bibliometrics:
Citation Count: 0

The emulation and functional validation are essential to the assessment of the correctness and performance of networks-on-chip architecture. A flexible hardware/software networks-on-chip open platform (NoCOP) emulation framework is designed and implemented for exploring the on-chip interconnection network architectures. An instruction set simulator and universal serial bus communicator control and configure ...
Keywords: chip, emulation, network architectures, network-on-, verification, FPGA, functional validation, on-chip interconnection, NoC, serial bus communication control, field programmable gate arrays, instruction set simulation, routers

5
September 2010 DSD '10: Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

Although adaptive routing algorithms promise higher communication performance, as compared to deterministic routing algorithms, they suffer from the out-of-order packet delivery problem. In the context of Network on Chip, the area and computational overhead of ordering packets at the destination is high and may reverse any gain achieved through the ...
Keywords: Network on Chip, Routing Algorithm, Router Design, Performance Analysis, Adaptivity, In-order packet delivery

6 published by ACM
May 2010 ACM Transactions on Architecture and Code Optimization (TACO): Volume 7 Issue 1, April 2010
Publisher: ACM
Bibliometrics:
Citation Count: 8
Downloads (6 Weeks): 1,   Downloads (12 Months): 18,   Downloads (Overall): 555

Full text available: PDFPDF
In this article, we investigate the Intellectual Property (IP) mapping problem that maps a given set of IP cores onto the tiles of a mesh-based Network-on-Chip (NoC) architecture such that the power consumption due to intercore communications is minimized. This IP mapping problem is considered under both bandwidth and latency ...
Keywords: bandwidth and latency constraints, network-on-chip (NoC), Low power, IP mapping

7
November 2009 Computers and Electrical Engineering: Volume 35 Issue 6, November, 2009
Publisher: Pergamon Press, Inc.
Bibliometrics:
Citation Count: 5

Many on-chip network circuit and architecture techniques are incompatible with modern design flows, making them unsuitable for use in systems-on-chip. This paper presents a networks-on-chip (NoC) architecture design space exploration method for multi-processor systems-on-chip architecture. The NoC architecture design space is designed with a Layer-Interactive-Building block (LIB) methodology that is ...
Keywords: IP cores, Multi-processor systems-on-chip, Networks-on-chip, Protocols

8
April 2009 ITNG '09: Proceedings of the 2009 Sixth International Conference on Information Technology: New Generations
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 2

The emulation and functional validation are essential to assessment of the correctness and performance of networks-on-chip architecture. A flexible hardware/software networks-on-chip open platform (NoCOP) emulation framework is designed and implemented for exploring the on-chip interconnection networks architecture. An instruction set simulator and universal serial bus communicator control and configure the ...
Keywords: networks-on-chip (NoC), multiprocessor systems-on-chip (MPSoC), emulation, FPGA



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