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 Dong Wang

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Bibliometrics: publication history
Average citations per article1.43
Citation Count10
Publication count7
Publication years2005-2016
Available for download1
Average downloads per article147.00
Downloads (cumulative)147
Downloads (12 Months)51
Downloads (6 Weeks)13
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1 published by ACM
January 2016 ACM Transactions on Architecture and Code Optimization (TACO): Volume 12 Issue 4, January 2016
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 13,   Downloads (12 Months): 51,   Downloads (Overall): 147

Full text available: PDFPDF
The efficacy of single instruction, multiple data (SIMD) architectures is limited when handling divergent control flows. This circumstance results in SIMD fragments using only a subset of the available lanes. We propose an iteration interleaving--based SIMD lane partition (IISLP) architecture that interleaves the execution of consecutive iterations and dynamically partitions ...
Keywords: SIMD, iteration interleaving, vector iteration, SIMD lane partition, instruction shuffle

2
May 2008 CISP '08: Proceedings of the 2008 Congress on Image and Signal Processing, Vol. 2 - Volume 02
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Multi-Core Digital Signal Processors (MC-DSPs) often suffer from limited memory bandwidth and long access latency caused by shared-memory structures. Data forwarding is an efficient data speculation technique to hide memory access latencies. This paper proposes a new Data Stream Clustered Forwarding (DSCF) technique for MC-DSPs in shared-memory structures. DSCF combines ...

3
March 2008 AICCSA '08: Proceedings of the 2008 IEEE/ACS International Conference on Computer Systems and Applications
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

In this paper, we propose a new digital signal processor architecture SPVA (Scalable Parallel VLIW architecture) for Software Defined Radio. The proposed architecture organizes function units into arithmetic units, and other units. The former are organized as SIMD clusters and the latter are organized as control clusters. Advantages of the ...

4
September 2007 HPCC'07: Proceedings of the Third international conference on High Performance Computing and Communications
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 0

This paper proposes a highly efficient MBRP parallel algorithm for H.264 encoder, which is based on the analysis of data dependencies in H.264 encoder. In the algorithm, the video frames are partitioned into several MB regions, each of which consists of several adjoining columns of macroblocks (MB), which could be ...

5
September 2007 HPCC '07: Proceedings of the 3rd international conference on High Performance Computing and Communications
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 9

This paper proposes a highly efficient MBRP parallel algorithm for H.264 encoder, which is based on the analysis of data dependencies in H.264 encoder. In the algorithm, the video frames are partitioned into several MB regions, each of which consists of several adjoining columns of macro-blocks (MB), which could be ...

6
September 2006 ACSAC'06: Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 0

Memory bandwidth and interface flexibility are often bottlenecks of embedded processors. The research about memory bandwidth optimization has become a hot topic. This paper introduces four new bandwidth optimization methods for External Memory Control Interface (EMCI) integrated in high performance digit signal processors (DSP), and aims at realization of the ...

7
December 2005 ICESS '05: Proceedings of the Second International Conference on Embedded Software and Systems
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

This paper introduces several important methods to design the embedded external memory interface (EMIF) for a high performance DSP (Digital Signal processor). Starting with the design specification of the EMIF, this paper introduces four important new design methods, i.e. width-scalable accessing, data buffers based on asynchronous FIFOs, token cycle method ...



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