Daniel A. Orozco
Daniel A. Orozco

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orozcoatudel.edu

  Affiliation history
Bibliometrics: publication history
Average citations per article3.44
Citation Count31
Publication count9
Publication years2009-2016
Available for download2
Average downloads per article260.50
Downloads (cumulative)521
Downloads (12 Months)48
Downloads (6 Weeks)0
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9 results found Export Results: bibtexendnoteacmrefcsv

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1
April 2016 International Journal of Parallel Programming: Volume 44 Issue 2, April 2016
Publisher: Kluwer Academic Publishers
Bibliometrics:
Citation Count: 0

This paper provides an extended description of the design and implementation of the Time Iterated Dependency Flow (TIDeFlow) execution model. TIDeFlow is a dataflow-inspired model that simplifies the scheduling of shared resources on many-core processors. To accomplish this, programs are specified as directed graphs and the dataflow model is extended ...
Keywords: Dependency graph, Iterated dataflow, TIDeFlow, Task pipelining, Codelets, Dataflow, Parallel execution models, Runtime system, Graph languages

2
May 2012 IPDPSW '12: Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 3

The recent evolution of many-core architectures has resulted in chips where the number of processor elements (PEs) are in the hundreds and continue to increase every day. In addition, many-core processors are more and more frequently characterized by the diversity of their resources and the way the sharing of those ...
Keywords: many-core architectures, dynamic scheduling, fine grain, low overhead, load balancing

3 published by ACM
May 2012 CF '12: Proceedings of the 9th conference on Computing Frontiers
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 0,   Downloads (12 Months): 8,   Downloads (Overall): 119

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This paper provides a discussion on the shortcomings of traditional static optimization techniques when used in the context of many-core architectures. We argue that these shortcomings are a result of the significantly different environment found in many-cores. We analyze previous attempts at optimization of Dense Matrix Multiplication (DMM) that failed ...
Keywords: dynamic scheduling, many-core architectures, scalability, percolation, parallel computer architure

4 published by ACM
January 2012 ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers: Volume 8 Issue 4, January 2012
Publisher: ACM
Bibliometrics:
Citation Count: 5
Downloads (6 Weeks): 0,   Downloads (12 Months): 40,   Downloads (Overall): 402

Full text available: PDFPDF
Advanced many-core CPU chips already have a few hundreds of processing cores (e.g., 160 cores in an IBM Cyclops-64 chip) and more and more processing cores become available as computer architecture progresses. The underlying runtime systems of such architectures need to efficiently serve hundreds of processors at the same time, ...
Keywords: parallel queue, FIFO queue, concurrent queues, Intrinsic throughput, manycore architectures, throughput, queue algorithms

5
October 2011 PACT '11: Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

The popularity of serial execution paradigms in the High Performance Computing (HPC) field greatly hinders the ability of computational scientists to develop and support massively parallel programs. Programmers are left with languages that are inadequate to express parallel constructs, being forced to take decisions that are not directly related to ...
Keywords: Dataflow, Dynamic dataflow, Macro dataflow, Parallel execution model, Parallel Runtime Systems, Task Management, Tasking framework, Manycore, Cyclops-64

6
October 2011 DFM '11: Proceedings of the 2011 First Workshop on Data-Flow Execution Models for Extreme Scale Computing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 8

The many-core revolution brought forward by recent advances in computer architecture has created immense challenges in the writing of parallel programs for High Performance Computing (HPC). Development of parallel HPC programs remains an art, and a universaldoctrine for synchronization, scheduling and execution in general has not been found for many-core/multi-core ...
Keywords: TIDeFlow, dataflow, execution model, runtime system, graph languages, codelets, iterated dataflow, dependency graph, parallel programming

7
August 2011 Euro-Par'11: Proceedings of the 17th international conference on Parallel processing - Volume Part II
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 0

Manycore architectures - hundreds to thousands of cores per processor - are seen by many as a natural evolution of multicore processors. To take advantage of this massive parallelism in practice requires a productive parallel programming model, and an efficient runtime for the scheduling and coordination of concurrent tasks. A ...

8
October 2010 LCPC'10: Proceedings of the 23rd international conference on Languages and compilers for parallel computing
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 2

This paper proposes tiling techniques based on data dependencies and not in code structure. The work presented here leverages and expands previous work by the authors in the domain of non traditional tiling for parallel applications. The main contributions of this paper are: (1) A formal description of tiling from ...

9
September 2009 ICPP '09: Proceedings of the 2009 International Conference on Parallel Processing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 8

This paper reports a study of mapping the Finite Difference Time Domain (FDTD) application to the IBM Cyclops-64 (C64) many-core chip architecture [1]. C64 is chosen for this study as it represents the current trend in computer architecture to develop a class of many-core architectures with distinct features e.g. software ...
Keywords: Bandwidth Reduction, Stencil Computations, Parallel Tiling, Code Optimization



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