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 Oscar Plata

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Average citations per article1.10
Citation Count11
Publication count10
Publication years2002-2015
Available for download1
Average downloads per article222.00
Downloads (cumulative)222
Downloads (12 Months)16
Downloads (6 Weeks)0
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10 results found Export Results: bibtexendnoteacmrefcsv

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1
September 2015 Procedia Computer Science: Volume 51 Issue C, September 2015
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 0

Transactional memory (TM) offers optimistic concurrency support in modern multicore archi- tectures, helping the programmers to extract parallelism when data dependence information is not statically available. This work presents ReduxSTM, a software TM system especially designed to extract parallelism from irregular applications. Commit management and conflict detection are tailored to ...
Keywords: Irregular application, Transactional memory, Reduction pattern, Thread-level speculation

2
October 2014 SBAC-PAD '14: Proceedings of the 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Signatures have been proposed in Hardware Transactional Memory (HTM) to represent read and write sets of transactions and decouple transaction conflict detection from private caches. Generally, signatures are implemented as Bloom filters that allow unbounded read/write sets to be summarized in bounded hardware, at the cost of address aliasing that ...

3
October 2014 SBAC-PAD '14: Proceedings of the 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Signatures have been proposed in transactional memory systems to represent read and write sets and to decouple transaction conflict detection from private caches or to accelerate it. Generally, signatures are implemented as Bloom filters that allow unbounded read/write sets to be summarized in bounded space at the cost of false ...
Keywords: Hardware transactional memory, Bloom filter, signatures, conflict detection, locality, multiset, asymmetric

4 published by ACM
August 2014 ACM Transactions on Architecture and Code Optimization (TACO): Volume 11 Issue 3, October 2014
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 0,   Downloads (12 Months): 16,   Downloads (Overall): 222

Full text available: PDFPDF
This article describes a transactional memory execution model intended to exploit maximum parallelism from sequential and multithreaded programs. A program code section is partitioned into chunks that will be mapped onto threads and executed transactionally. These transactions run concurrently and out of order, trying to exploit maximum parallelism but managed ...
Keywords: concurrency exploitation, dependence analysis, Transactional memory, optimistic concurrency, program parallelization

5
October 2013 SBAC-PAD '13: Proceedings of the 2013 25th International Symposium on Computer Architecture and High Performance Computing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Reductions are common operations in many real-world applications that may be responsible for a significant part of the computing time. Modern compilers implement parallel reductions by combining privatization, atomic operations and/or locks. In this paper we analyze how to address reductions in the transactional memory (TM) model, which is flourishing ...
Keywords: Transactional memory, reduction operations, partial reductions, selective privatization

6
March 2013 IEEE Transactions on Parallel and Distributed Systems: Volume 24 Issue 3, March 2013
Publisher: IEEE Press
Bibliometrics:
Citation Count: 0

Transactional Memory (TM) systems must track memory accesses made by concurrent transactions in order to detect conflicts. Many TM implementations use signatures for this purpose, which summarize reads and writes in fixed-size bit registers at the cost of false positives (detection of nonexisting conflicts). Signatures are commonly implemented as two ...
Keywords: Random access memory,Logic gates,Hardware,Arrays,Indexes,Registers,Programming,asymmetric,Hardware transactional memory,Bloom filter,signatures,conflict detection,locality,multiset

7
February 2013 IEEE Transactions on Computers: Volume 62 Issue 2, February 2013
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

Transactional Memory (TM) is an alternative to conventional multithreaded programming to ease the writing of concurrent programs. In the context of unbounded TM, concurrent threads may use hardware signatures to record all the memory addresses issued inside a transaction to detect conflicts. Signatures are usually implemented as per-thread fixed hardware ...
Keywords: Hardware,Null space,Indexes,Vectors,Instruction sets,Arrays,Proposals,memory locality,Hardware Transactional Memory,signatures,bloom filters,H3 hashing

8
August 2008 IEEE Transactions on Education: Volume 51 Issue 3, August 2008
Publisher: IEEE Press
Bibliometrics:
Citation Count: 0

This paper presents a tool that simulates a reconfigurable cache whose parameters can be changed at runtime through a special instruction at the instruction set architecture (ISA) level. The proposed tool simulates a cache system that can be reconfigured within a variety of 298 combinations of cache capacity, number of ...
Keywords: education, simulation software, reconfigurable cache design, Cache memories, computer-aided instruction

9
September 2004 LCPC'04: Proceedings of the 17th international conference on Languages and Compilers for High Performance Computing
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 2

The approach presented in this paper focus on detecting data dependences induced by heap-directed pointers on loops that access dynamic data structures. Knowledge about the shape of the data structure accessible from a heap-directed pointer, provides critical information for disambiguating heap accesses originating from it. Our approach is based on ...

10
January 2002 EUROMICRO-PDP'02: Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Different parallelization techniques for reductions have been proposed elsewhere, that we have classified in this paper into two classes: LPO (Loop Partitioning Oriented techniques) and DPO (Data Partitioning Oriented techniques). We have analyzed both classes in terms of a set of performance properties: data locality, memory overhead, parallelism and workload ...



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