Author image not provided
 Antonio Garcia-Guirado

Authors:
Add personal information
  Affiliation history
Bibliometrics: publication history
Average citations per article1.67
Citation Count5
Publication count3
Publication years2010-2012
Available for download1
Average downloads per article326.00
Downloads (cumulative)326
Downloads (12 Months)12
Downloads (6 Weeks)2
SEARCH
ROLE
Arrow RightAuthor only


AUTHOR'S COLLEAGUES
See all colleagues of this author

SUBJECT AREAS
See all subject areas




BOOKMARK & SHARE


3 results found Export Results: bibtexendnoteacmrefcsv

Result 1 – 3 of 3
Sort by:

1 published by ACM
January 2012 ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers: Volume 8 Issue 4, January 2012
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 2,   Downloads (12 Months): 12,   Downloads (Overall): 326

Full text available: PDFPDF
Many-core tiled CMP proposals often assume a partially shared last level cache (LLC) since this provides a good compromise between access latency and cache utilization. In this paper, we propose a novel way to map memory addresses to LLC banks that takes into account the average distance between the banks ...
Keywords: cache, distance to cache, power, Last-level cache, static block mapping

2
September 2011 ICPP '11: Proceedings of the 2011 International Conference on Parallel Processing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 2

As the number of cores in a chip increases, power consumption is becoming a major constraint in the design of chip multiprocessors. At the same time, server consolidation is gaining importance to take advantage of such a number of cores. Our goal is to alleviate this constraint by reducing the ...

3
October 2010 SBAC-PAD '10: Proceedings of the 2010 22nd International Symposium on Computer Architecture and High Performance Computing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

Server consolidation is commonly used today to make the most out of all the cores of a chip multiprocessor by running several virtual machines (VMs) on it. Cache coherence protocols can be adapted to take advantage of such an scenario. In this line, Virtual Hierarchies (VHs) use two levels of ...



The ACM Digital Library is published by the Association for Computing Machinery. Copyright © 2018 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us