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 Bertrandle Gal

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Average citations per article1.29
Citation Count9
Publication count7
Publication years2011-2016
Available for download3
Average downloads per article114.00
Downloads (cumulative)342
Downloads (12 Months)26
Downloads (6 Weeks)2
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7 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
September 2016 ACM Transactions on Reconfigurable Technology and Systems (TRETS): Volume 10 Issue 1, December 2016
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 24,   Downloads (12 Months): 51,   Downloads (Overall): 118

Full text available: PDFPDF
Embedded systems are being increasingly network interconnected. They are required to interact with their environment through text-based protocol messages. Parsing such messages is control dominated. The work presented in this article attempts to accelerate message parsers using a codesign-based approach. We propose a generic architecture associated with an automated design ...
Keywords: Automated design methodology, FPGA, FSM, LEON-3, System on Chip, dynamic reconfiguration

2
September 2015 LCPC 2015: Revised Selected Papers of the 28th International Workshop on Languages and Compilers for Parallel Computing - Volume 9519
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 0

Error Correction Code decoding algorithms for consumer products such as Internet of Things IoT devices are usually implemented as dedicated hardware circuits. As processors are becoming increasingly powerful and energy efficient, there is now a strong desire to perform this processing in software to reduce production costs and time to ...
Keywords: Domain specific language, Code generation, Polar codes, SIMDization, Successive cancellation decoding, Error correction codes, Generic programming

3 published by ACM
March 2014 ACM Transactions on Embedded Computing Systems (TECS) - Regular Papers: Volume 13 Issue 4, November 2014
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 11,   Downloads (Overall): 219

Full text available: PDFPDF
Rapid prototyping is an important step in the development and the verification of computationally demanding tasks of digital communication systems, such as Forward Error Correction (FEC) decoding. The goal is to replace time-consuming simulations based on abstract models of the system with real-time experiments under real-world conditions. GPU-like architecture is ...
Keywords: FEC techniques, FPGA implementation, GPU-like architecture, LDPC codes, MIPS processor, SIMD matrix, signal processing systems

4
November 2013 Journal of Signal Processing Systems: Volume 73 Issue 2, November 2013
Publisher: Kluwer Academic Publishers
Bibliometrics:
Citation Count: 0

This paper presents a novel hardware architecture for the real-time high-throughput implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard. A parallel filtering order of six units is proposed according to the H.264/AVC standard. With a parallel filtering order (fully compliant with H.264/AVC) and a ...
Keywords: Filtering order, H.264/AVC video coding, ASIC, Deblocking filter

5
January 2012 VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation: Volume 2012, January 2012
Publisher: Hindawi Limited
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 3,   Downloads (Overall): 11

Full text available: PDFPDF
Decimation filters are widely used in communication-embedded systems. In fact, decimation filters are useful for implementing channel filtering or selection with low-computation complexity requirements. Many multistandard receiver designs that are required in ubiquitous embedded systems are based on a cascade of decimation filter processing. Filter number and implementation architectures have ...

6
May 2011 IPDPSW '11: Proceedings of the 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 2

This paper presents a reconfigurable Multi-Core Crypto-Processor MCCP) especially designed to secure multi-channel and multi-standard communication systems. Such component meets many constraints like high throughput and flexibility. In contrast, a classical mono-core approach either provides limited throughput or does not allow simple management of multi-channel streams. Nevertheless, parallelism is not ...

7
March 2011 Journal of Signal Processing Systems: Volume 62 Issue 3, March 2011
Publisher: Kluwer Academic Publishers
Bibliometrics:
Citation Count: 1

Multimedia applications such as video and image processing are often characterized as computation intensive applications. For these applications the word-length of data and instructions is different throughout the application. Generating hardware architectures is not a straightforward task since it requires a deep word-length analysis in order to properly determine what ...
Keywords: Resource sharing, Hardware design, High-level synthesis, Data sizing



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