Author image not provided
 Daniel Lustig

Authors:
Add personal information
  Affiliation history
Bibliometrics: publication history
Average citations per article7.62
Citation Count99
Publication count13
Publication years2011-2017
Available for download10
Average downloads per article360.20
Downloads (cumulative)3,602
Downloads (12 Months)1,183
Downloads (6 Weeks)87
SEARCH
ROLE
Arrow RightAuthor only


AUTHOR'S COLLEAGUES
See all colleagues of this author

SUBJECT AREAS
See all subject areas




BOOKMARK & SHARE


13 results found Export Results: bibtexendnoteacmrefcsv

Result 1 – 13 of 13
Sort by:

1 published by ACM
October 2017 MICRO-50 '17: Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 19,   Downloads (12 Months): 126,   Downloads (Overall): 126

Full text available: PDFPDF
Paramount to the viability of a parallel architecture is the correct implementation of its memory consistency model (MCM). Although tools exist for verifying consistency models at several design levels, a problematic verification gap exists between checking an abstract microarchitectural specification of a consistency model and verifying that the actual processor ...
Keywords: RTL, automated verification, memory consistency models, SVA

2
September 2017
Bibliometrics:
Citation Count: 0

This book provides computer engineers, academic researchers, new graduate students, and seasoned practitioners an end-to-end overview of virtual memory. We begin with a recap of foundational concepts and discuss not only state-of-the-art virtual memory hardware and software support available today, but also emerging research trends in this space. The span ...

3 published by ACM
April 2017 ASPLOS '17: Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 19,   Downloads (12 Months): 241,   Downloads (Overall): 241

Full text available: PDFPDF
The memory consistency model is a fundamental part of any shared memory architecture or programming model. Modern weak memory models are notoriously difficult to define and to implement correctly. Most real-world programming languages, compilers, and (micro)architectures therefore rely heavily on black-box testing methodologies. The success of such techniques requires that ...
Keywords: litmus tests, memory consistency models, synchronization, synthesis
Also published in:
May 2017  ACM SIGPLAN Notices - ASPLOS '17: Volume 52 Issue 4, April 2017 May 2017  ACM SIGARCH Computer Architecture News - Asplos'17: Volume 45 Issue 1, March 2017

4 published by ACM
April 2017 ASPLOS '17: Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 16,   Downloads (12 Months): 209,   Downloads (Overall): 209

Full text available: PDFPDF
Memory consistency models (MCMs) which govern inter-module interactions in a shared memory system, are a significant, yet often under-appreciated, aspect of system design. MCMs are defined at the various layers of the hardware-software stack, requiring thoroughly verified specifications, compilers, and implementations at the interfaces between layers. Current verification techniques evaluate ...
Keywords: here, keywords, separated by semi-colons
Also published in:
May 2017  ACM SIGPLAN Notices - ASPLOS '17: Volume 52 Issue 4, April 2017 May 2017  ACM SIGARCH Computer Architecture News - Asplos'17: Volume 45 Issue 1, March 2017

5 published by ACM
March 2016 ASPLOS '16: Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems
Publisher: ACM
Bibliometrics:
Citation Count: 7
Downloads (6 Weeks): 9,   Downloads (12 Months): 155,   Downloads (Overall): 305

Full text available: PDFPDF
Modern computer systems include numerous compute elements, from CPUs to GPUs to accelerators. Harnessing their full potential requires well-defined, properly-implemented memory consistency models (MCMs), and low-level system functionality such as virtual memory and address translation (AT). Unfortunately, it is difficult to specify and implement hardware-OS interactions correctly; in the past, ...
Keywords: computer architecture, virtual memory, address translation, verification, memory consistency models
Also published in:
June 2016  ACM SIGPLAN Notices - ASPLOS '16: Volume 51 Issue 4, April 2016 July 2016  ACM SIGARCH Computer Architecture News - ASPLOS'16: Volume 44 Issue 2, May 2016

6 published by ACM
December 2015 MICRO-48: Proceedings of the 48th International Symposium on Microarchitecture
Publisher: ACM
Bibliometrics:
Citation Count: 5
Downloads (6 Weeks): 4,   Downloads (12 Months): 58,   Downloads (Overall): 170

Full text available: PDFPDF
In parallel systems, memory consistency models and cache coherence protocols establish the rules specifying which values will be visible to each instruction of parallel programs. Despite their central importance, verifying their correctness has remained a major challenge, due both to informal or incomplete specifications and to difficulties in scaling verification ...

7 published by ACM
September 2015 ACM Transactions on Computer Systems (TOCS): Volume 33 Issue 3, September 2015
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 6,   Downloads (12 Months): 82,   Downloads (Overall): 337

Full text available: PDFPDF
There has been recent interest in exploring the acceleration of nonvectorizable workloads with spatially programmed architectures that are designed to efficiently exploit pipeline parallelism. Such an architecture faces two main problems: how to efficiently control each processing element (PE) in the system, and how to facilitate inter-PE communication without the ...
Keywords: Spatial programming, reconfigurable accelerators

8 published by ACM
June 2015 ISCA '15: Proceedings of the 42nd Annual International Symposium on Computer Architecture
Publisher: ACM
Bibliometrics:
Citation Count: 6
Downloads (6 Weeks): 5,   Downloads (12 Months): 60,   Downloads (Overall): 357

Full text available: PDFPDF
Architectural heterogeneity is increasing: numerous products and studies have proven the benefits of combining cores and accelerators with varying ISAs into a single system. However, an underappreciated barrier to unlocking the full potential of heterogeneity is the need to specify and to reconcile differences in memory consistency models across layers ...
Also published in:
January 2016  ACM SIGARCH Computer Architecture News - ISCA'15: Volume 43 Issue 3, June 2015

9
December 2014 MICRO-47: Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 9
Downloads (6 Weeks): 0,   Downloads (12 Months): 25,   Downloads (Overall): 124

Full text available: PDFPDF
We present PipeCheck, a methodology and automated tool for verifying that a particular microarchitecture correctly implements the consistency model required by its architectural specification. PipeCheck adapts the notion of a "happens before" graph from architecture-level analysis techniques to the microarchitecture space. Each node in the "micro architecturally happens before" (μhb) ...

10 published by ACM
June 2013 ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture
Publisher: ACM
Bibliometrics:
Citation Count: 18
Downloads (6 Weeks): 5,   Downloads (12 Months): 178,   Downloads (Overall): 1,191

Full text available: PDFPDF
In this paper, we present triggered instructions , a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without explicit branch instructions. They also allow efficient reactivity to inter-PE communication ...
Keywords: reconfigurable accelerators, spatial programming
Also published in:
June 2013  ACM SIGARCH Computer Architecture News - ICSA '13: Volume 41 Issue 3, June 2013

11 published by ACM
April 2013 ACM Transactions on Architecture and Code Optimization (TACO): Volume 10 Issue 1, April 2013
Publisher: ACM
Bibliometrics:
Citation Count: 10
Downloads (6 Weeks): 4,   Downloads (12 Months): 49,   Downloads (Overall): 542

Full text available: PDFPDF
Translation Lookaside Buffers (TLBs) are critical to overall system performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as Chip MultiProcessors (CMPs) become ubiquitous, TLB design and performance must be reevaluated. Our article begins by performing a thorough TLB performance evaluation of sequential and ...
Keywords: simulation, Translation lookaside buffer, TLB prefetching, performance evaluation, shared last-level TLB

12
February 2013 HPCA '13: Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 13

GPUs are seeing increasingly widespread use for general purpose computation due to their excellent performance for highly-parallel, throughput-oriented applications. For many workloads, however, the performance benefits of offloading are hindered by the large and unpredictable overheads of launching GPU kernels and of transferring data between CPU and GPU.

13
February 2011 HPCA '11: Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 24

Translation Lookaside Buffers (TLBs) are critical to processor performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as chip multiprocessors (CMPs) become ubiquitous, TLB design must be re-evaluated. This paper is the first to propose and evaluate shared last-level (SLL) TLBs as an alternative ...



The ACM Digital Library is published by the Association for Computing Machinery. Copyright © 2018 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us