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 Vaishnav Srinivas

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Average citations per article0.83
Citation Count5
Publication count6
Publication years2011-2017
Available for download4
Average downloads per article133.25
Downloads (cumulative)533
Downloads (12 Months)212
Downloads (6 Weeks)19
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6 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
June 2017 ACM Transactions on Architecture and Code Optimization (TACO): Volume 14 Issue 2, July 2017
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 17,   Downloads (12 Months): 193,   Downloads (Overall): 271

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Historically, server designers have opted for simple memory systems by picking one of a few commoditized DDR memory products. We are already witnessing a major upheaval in the off-chip memory hierarchy, with the introduction of many new memory products—buffer-on-board, LRDIMM, HMC, HBM, and NVMs, to name a few. Given the ...
Keywords: DRAM, Memory, NVM, interconnects, tools

2
May 2017 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Volume 36 Issue 5, May 2017
Publisher: IEEE Press
Bibliometrics:
Citation Count: 0

Photonic network-on-chip (PNoC) is a promising candidate to replace traditional electrical NoC in manycore systems that require substantial bandwidths. The photonic links in the PNoC comprise laser sources, optical ring resonators, passive waveguides, and photodetectors. Reliable link operation requires laser sources and ring resonators to have matching optical frequencies. However, ...

3
March 2016 DATE '16: Proceedings of the 2016 Conference on Design, Automation & Test in Europe
Publisher: EDA Consortium
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 3,   Downloads (Overall): 3

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Many-core chip architectures are now feasible, but the power consumption of electrical networks-on-chip does not scale well. Silicon photonic NoCs (PNoCs) are more scalable and power efficient, but floorplan optimization is challenging. Prior work optimizes PNoC floorplans through simultaneous place and route, but does not address cross-layer effects that span ...

4 published by ACM
November 2012 ICCAD '12: Proceedings of the International Conference on Computer-Aided Design
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 1,   Downloads (12 Months): 9,   Downloads (Overall): 126

Full text available: PDFPDF
We describe CACTI-IO, an extension to CACTI [4] that includes power, area and timing models for the IO and PHY of the off-chip memory interface for various server and mobile configurations. CACTI-IO enables design space exploration of the off-chip IO along with the DRAM and cache parameters. We describe the ...
Keywords: CACTI, DRAM, IO, memory interface, power and timing models

5
June 2011 SLIP '11: Proceedings of the International Workshop on System Level Interconnect Prediction
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

A variety of interconnect technologies and standards (DIMMs, MCP, POP, stacked-die and 3D-stack) enable a controller IC to communicate with an external SDRAM, or with multiple SDRAMs over a shared interconnect. Low-power requirements have driven mobile controllers to mobile-SDRAM (LPDDR) memory solutions. However, LPDDR configurations do not scale to match ...

6
June 2011 SLIP '11: Proceedings of the System Level Interconnect Prediction Workshop
Publisher: IEEE Press
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 0,   Downloads (12 Months): 7,   Downloads (Overall): 130

Full text available: PDFPDF
A variety of interconnect technologies and standards (DIMMs, MCP, POP, stacked-die and 3D-stack) enable a controller IC to communicate with an external SDRAM, or with multiple SDRAMs over a shared interconnect. Low-power requirements have driven mobile controllers to mobile-SDRAM (LPDDR) memory solutions. However, LPDDR configurations do not scale to match ...
Keywords: 3D, DDR, IO, LPDDR, SDRAM, memory configuration, mobile, serial memory, tablet, wide IO



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