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 Cheng Yuan Michael Wang

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Average citations per article8.40
Citation Count42
Publication count5
Publication years2012-2016
Available for download5
Average downloads per article599.40
Downloads (cumulative)2,997
Downloads (12 Months)576
Downloads (6 Weeks)46
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1 published by ACM
December 2016 ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section of IDEA: Integrating Dataflow, Embedded Computing, and Architecture: Volume 22 Issue 2, March 2017
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 7,   Downloads (12 Months): 124,   Downloads (Overall): 125

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Flash memory is widely used in mobile phones to store contact information, application files, and other types of data. In an operating system, the buffer cache keeps the I/O blocks in dynamic random access memory (DRAM) to reduce the slow flash accesses. However, in smartphones, we observed two issues which ...
Keywords: Buffer cache, smartphone, phase change memory (PCM)

2 published by ACM
June 2016 ACM Transactions on Design Automation of Electronic Systems (TODAES): Volume 22 Issue 1, December 2016
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 5,   Downloads (12 Months): 81,   Downloads (Overall): 150

Full text available: PDFPDF
Improving PCM endurance is a fundamental issue when it is considered as an alternative to replace DRAM as main memory. Memory-based wear leveling (WL) is an effective way to improve PCM endurance, but its major challenge is how to efficiently determine the appropriate memory pages for allocation or swapping. In ...
Keywords: Phase change memory, endurance, wear leveling

3 published by ACM
June 2015 ACM Transactions on Architecture and Code Optimization (TACO): Volume 12 Issue 2, July 2015
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 4,   Downloads (12 Months): 24,   Downloads (Overall): 129

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DRAMs are used as the main memory in most computing systems today. Studies show that DRAMs contribute to a significant part of overall system power consumption. One of the main challenges in low-power DRAM design is the inevitable refresh process. Due to process variation, memory cells exhibit retention time variations. ...
Keywords: retention errors, error control codes, DRAM-based main memory, refresh power reduction

4 published by ACM
February 2014 ASPLOS '14: Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
Publisher: ACM
Bibliometrics:
Citation Count: 21
Downloads (6 Weeks): 24,   Downloads (12 Months): 289,   Downloads (Overall): 2,135

Full text available: PDFPDF
Emerging non-volatile memory (NVM) technologies have gained a lot of attention recently. The byte-addressability and high density of NVM enable computer architects to build large-scale main memory systems. NVM has also been shown to be a promising alternative to conventional persistent store. With NVM, programmers can persistently retain in-memory data ...
Keywords: memory management, non-volatile memory, refresh, resistance drift, resistance distribution, consistency, memory scheduler, phase-change memory, durability, storage-class memory
Also published in:
April 2014  ACM SIGPLAN Notices - ASPLOS '14: Volume 49 Issue 4, April 2014 April 2014  ACM SIGARCH Computer Architecture News - ASPLOS '14: Volume 42 Issue 1, March 2014

5 published by ACM
June 2012 DAC '12: Proceedings of the 49th Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 20
Downloads (6 Weeks): 6,   Downloads (12 Months): 58,   Downloads (Overall): 458

Full text available: PDFPDF
Improving the endurance of PCM is a fundamental issue when the technology is considered as an alternative to main memory usage. In the design of memory-based wear leveling approaches, a major challenge is how to efficiently determine the appropriate memory pages for allocation or swapping. In this paper, we present ...
Keywords: endurance, memory management, wear-leveling, phase change memory



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