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 Kevin Chang

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Average citations per article14.25
Citation Count114
Publication count8
Publication years2012-2017
Available for download5
Average downloads per article358.40
Downloads (cumulative)1,792
Downloads (12 Months)616
Downloads (6 Weeks)97
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8 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
June 2017 Proceedings of the ACM on Measurement and Analysis of Computing Systems: Volume 1 Issue 1, June 2017
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 20,   Downloads (12 Months): 91,   Downloads (Overall): 91

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The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy consumption. We would like to reduce the DRAM supply voltage more aggressively, to further ...
Keywords: memory latency, performance, dram characterization, energy, reliability, voltage reduction, memory systems, dram

2 published by ACM
June 2017 SIGMETRICS '17 Abstracts: Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems
Publisher: ACM
Bibliometrics:
Citation Count: 5
Downloads (6 Weeks): 17,   Downloads (12 Months): 78,   Downloads (Overall): 78

Full text available: PDFPDF
The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy consumption. We would like to reduce the DRAM supply voltage more aggressively, to further ...
Keywords: DRAM, DRAM characterization, memory systems, memory latency, performance, energy, reliability, voltage reduction
Also published in:
September 2017  ACM SIGMETRICS Performance Evaluation Review - Performance evaluation review: Volume 45 Issue 1, June 2017

3 published by ACM
June 2016 SIGMETRICS '16: Proceedings of the 2016 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Science
Publisher: ACM
Bibliometrics:
Citation Count: 11
Downloads (6 Weeks): 21,   Downloads (12 Months): 187,   Downloads (Overall): 351

Full text available: PDFPDF
Long DRAM latency is a critical performance bottleneck in current systems. DRAM access latency is defined by three fundamental operations that take place within the DRAM cell array: (i) activation of a memory row, which opens the row to perform accesses; (ii) precharge, which prepares the cell array for the ...
Keywords: dram, dram errors, memory latency, process variation
Also published in:
June 2016  ACM SIGMETRICS Performance Evaluation Review - Performance evaluation review: Volume 44 Issue 1, June 2016

4
May 2016 Parallel Computing: Volume 54 Issue C, May 2016
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 0

This paper is the first to introduce a scalable and energy-efficient hierarchical ring design that relies on deflection routing and guarantees deadlock- and livelock-free packet delivery.We identify key drawbacks of previous hierarchical ring network designs with respect to scalability, performance and energy efficiency.We propose a new hierarchical ring network design ...
Keywords: Network on Chip, Parallelism, Interconnect

5 published by ACM
January 2016 ACM Transactions on Architecture and Code Optimization (TACO): Volume 12 Issue 4, January 2016
Publisher: ACM
Bibliometrics:
Citation Count: 8
Downloads (6 Weeks): 29,   Downloads (12 Months): 158,   Downloads (Overall): 334

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Modern SoCs integrate multiple CPU cores and hardware accelerators (HWAs) that share the same main memory system, causing interference among memory requests from different agents. The result of this interference, if it is not controlled well, is missed deadlines for HWAs and low CPU performance. Few previous works have tackled ...
Keywords: real-time systems, scheduling, Hardware accelerators, memory controller, deadline, heterogeneous systems, multicore, performance, GPUs, main memory, system-on-a-chip

6
October 2014 SBAC-PAD '14: Proceedings of the 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 8

Hierarchical ring networks, which hierarchically connect multiple levels of rings, have been proposed in the past to improve the scalability of ring interconnects, but past hierarchical ring designs sacrifice some of the key benefits of rings by reintroducing more complex in-ring buffering and buffered flow control. Our goal in this ...

7
June 2012 ISCA '12: Proceedings of the 39th Annual International Symposium on Computer Architecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 55
Downloads (6 Weeks): 9,   Downloads (12 Months): 103,   Downloads (Overall): 939

Full text available: PDFPDF
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from the CPU cores, leading to low system performance and starvation of CPU cores. Unfortunately, state-of-the-art application-aware memory scheduling algorithms are ineffective ...
Also published in:
September 2012  ACM SIGARCH Computer Architecture News - ISCA '12: Volume 40 Issue 3, June 2012

8
May 2012 NOCS '12: Proceedings of the 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 27

A conventional Network-on-Chip (NoC) router uses input buffers to store in-flight packets. These buffers improve performance, but consume significant power. It is possible to bypass these buffers when they are empty, reducing dynamic power, but static buffer power, and dynamic power when buffers are utilized, remain. To improve energy efficiency, ...



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