Mark Gottscho
Mark Gottscho

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mgottschoatucla.edu

  Affiliation history
Bibliometrics: publication history
Average citations per article3.13
Citation Count25
Publication count8
Publication years2012-2017
Available for download6
Average downloads per article152.33
Downloads (cumulative)914
Downloads (12 Months)169
Downloads (6 Weeks)28
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8 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
September 2017 ACM Transactions on Embedded Computing Systems (TECS) - Special Issue ESWEEK 2017, CASES 2017, CODES + ISSS 2017 and EMSOFT 2017: Volume 16 Issue 5s, October 2017
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 19,   Downloads (12 Months): 63,   Downloads (Overall): 63

Full text available: PDFPDF
IoT devices need reliable hardware at low cost. It is challenging to efficiently cope with both hard and soft faults in embedded scratchpad memories. To address this problem, we propose a two-step approach: FaultLink and Software-Defined Error-Localizing Codes (SDELC). FaultLink avoids hard faults found during testing by generating a custom-tailored ...
Keywords: defects, fault tolerance, approximate computing, ECC, IoT, Scratchpad memory, soft errors

2
March 2016 DATE '16: Proceedings of the 2016 Conference on Design, Automation & Test in Europe
Publisher: EDA Consortium
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 0,   Downloads (Overall): 1

Full text available: PDFPDF
High-performance chips require many power pins to support large currents, which increases fabrication cost, limits scalability, and degrades power efficiency. Multi-story serial power distribution networks (PDNs) are a promising approach to reducing pin counts and power losses. We study the feasibility of 2-story PDNs for graphics processing units (GPUs). These ...

3 published by ACM
August 2015 ACM Transactions on Architecture and Code Optimization (TACO): Volume 12 Issue 3, October 2015
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 3,   Downloads (12 Months): 37,   Downloads (Overall): 185

Full text available: PDFPDF
Fault-Tolerant Voltage-Scalable (FTVS) SRAM cache architectures are a promising approach to improve energy efficiency of memories in the presence of nanoscale process variation. Complex FTVS schemes are commonly proposed to achieve very low minimum supply voltages, but these can suffer from high overheads and thus do not always offer the ...
Keywords: energy proportionality, fault-tolerant voltage scaling, block disable, variability-aware, resizable cache, Process variation, low power, nanoscale technology

4
October 2014 HotPower'14: Proceedings of the 6th USENIX conference on Power-Aware Computing and Systems
Publisher: USENIX Association
Bibliometrics:
Citation Count: 0

Prior battery-aware systems research has focused on discharge power management in order to maximize the usable battery lifetime of a device. In order to achieve the vision of perpetual mobile device operation, we propose that software also needs to carefully consider the process of battery charging. This is because the ...

5 published by ACM
June 2014 DAC '14: Proceedings of the 51st Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 8
Downloads (6 Weeks): 1,   Downloads (12 Months): 16,   Downloads (Overall): 239

Full text available: PDFPDF
With memories continuing to dominate the area, power, cost and performance of a design, there is a critical need to provision reliable, high-performance memory bandwidth for emerging applications. Memories are susceptible to degradation and failures from a wide range of manufacturing, operational and environmental effects, requiring a multi-layer hardware/software approach ...

6 published by ACM
June 2014 DAC '14: Proceedings of the 51st Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 7
Downloads (6 Weeks): 4,   Downloads (12 Months): 38,   Downloads (Overall): 241

Full text available: PDFPDF
Complicated approaches to fault-tolerant voltage-scalable (FTVS) SRAM cache architectures can suffer from high overheads. We propose static (SPCS) and dynamic (DPCS) variants of power/capacity scaling, a simple and low-overhead fault-tolerant cache architecture that utilizes insights gained from our 45nm SOI test chip. Our mechanism combines multi-level voltage scaling with power ...

7 published by ACM
October 2012 CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Publisher: ACM
Bibliometrics:
Citation Count: 8
Downloads (6 Weeks): 0,   Downloads (12 Months): 14,   Downloads (Overall): 184

Full text available: PDFPDF
ITRS predicts that over the next decade, hardware power variation will increase at alarming rates. As a result, designers must build software that can adapt to and exploit these variations to reduce power consumption and improve system performance. This paper presents ViPZonE, a system-level solution that opportunistically exploits DRAM power ...
Keywords: dram, memory management, variability, power

8
June 2012 IEEE Embedded Systems Letters: Volume 4 Issue 2, June 2012
Publisher: IEEE Press
Bibliometrics:
Citation Count: 0

Technology scaling has led to significant variability in chip performance and power consumption. In this work, we measured and analyzed the power variability in dynamic random access memories (DRAMs). We tested 22 double date rate third generation (DDR3) dual inline memory modules (DIMMs), and found that power usage in DRAMs ...



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