ACM Transactions on Architecture and Code Optimization (TACO): Volume 12 Issue 4, January 2016
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The efficacy of single instruction, multiple data (SIMD) architectures is limited when handling divergent control flows. This circumstance results in SIMD fragments using only a subset of the available lanes. We propose an iteration interleaving--based SIMD lane partition (IISLP) architecture that interleaves the execution of consecutive iterations and dynamically partitions ...
SIMD, iteration interleaving, vector iteration, SIMD lane partition, instruction shuffle
ACSAC'07: Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Multi-core Digital Signal Processors (DSP) have significant requirements on data storage and memory performance for high performance embedded applications. Scratch-pad memories (SPM) are low capacity high-speed on-chip memories mapped with global addresses, which are preferred by embedded applications than traditional caches due to their better real-time characterization. We construct a ...