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 Xiaowen Chen

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Average citations per article0.00
Citation Count0
Publication count2
Publication years2007-2016
Available for download1
Average downloads per article147.00
Downloads (cumulative)147
Downloads (12 Months)51
Downloads (6 Weeks)13
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January 2016 ACM Transactions on Architecture and Code Optimization (TACO): Volume 12 Issue 4, January 2016
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 13,   Downloads (12 Months): 51,   Downloads (Overall): 147

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The efficacy of single instruction, multiple data (SIMD) architectures is limited when handling divergent control flows. This circumstance results in SIMD fragments using only a subset of the available lanes. We propose an iteration interleaving--based SIMD lane partition (IISLP) architecture that interleaves the execution of consecutive iterations and dynamically partitions ...
Keywords: SIMD, iteration interleaving, vector iteration, SIMD lane partition, instruction shuffle

2
August 2007 ACSAC'07: Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Publisher: Springer-Verlag
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Citation Count: 0

Multi-core Digital Signal Processors (DSP) have significant requirements on data storage and memory performance for high performance embedded applications. Scratch-pad memories (SPM) are low capacity high-speed on-chip memories mapped with global addresses, which are preferred by embedded applications than traditional caches due to their better real-time characterization. We construct a ...



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