BOOKMARK & SHARE
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Volume 33 Issue 3, March 2014
Publisher: IEEE Press
The ever-intensifying time-to-market pressure imposes great challenges on the pre-silicon design phase of hardware. Before the tape-out, a pre-silicon design has to be thoroughly inspected by time-consuming functional verification and code review to exclude bugs. For functional verification and code review, a critical issue determining their efficiency is the allocation ...
IEEE Transactions on Computers: Volume 62 Issue 9, September 2013
Publisher: IEEE Computer Society
To efficiently and effectively debug silicon bugs, a promising solution is to determinize the chip, so that the buggy silicon behaviors can be faithfully reproduced on a RTL simulator. In this paper, we propose a novel scheme, named LDet, to determinize a chip through removing the nondeterminism in transfers crossing ...
Clocks,Synchronization,Debugging,Receivers,Silicon,Time frequency analysis,Hardware,FIFO,Determinism,chip,synchronization,clock domain crossing,global clock,asynchronous,heterochronous,post-silicon debugging
ACM Transactions on Architecture and Code Optimization (TACO): Volume 10 Issue 1, April 2013
Citation Count: 1
Downloads (6 Weeks): 3, Downloads (12 Months): 17, Downloads (Overall): 350
Full text available:
Debugging parallel programs is a well-known difficult problem. A promising method to facilitate debugging parallel programs is using hardware support to achieve deterministic replay on a Chip Multi-Processor (CMP). As a Design-For-Debug (DFD) feature, a practical hardware-assisted deterministic replay scheme should have low design and verification costs, as well as ...
CMP, design for debug, global clock, physical time order, Deterministic replay, pending period
Microprocessors & Microsystems: Volume 37 Issue 1, February, 2013
Publisher: Elsevier Science Publishers B. V.
Predictive modeling is an emerging methodology for microarchitectural design space exploration. However, this method suffers from high costs to construct predictive models, especially when unseen programs are employed in performance evaluation. In this paper, we propose a fast predictive model-based approach for microarchitectural design space exploration. The key of our ...
Model tree, Predictive models, Microarchitecture, Design space exploration