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 Younghoon Son

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Bibliometrics: publication history
Average citations per article6.20
Citation Count31
Publication count5
Publication years2013-2014
Available for download5
Average downloads per article487.00
Downloads (cumulative)2,435
Downloads (12 Months)318
Downloads (6 Weeks)26
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5 results found Export Results: bibtexendnoteacmrefcsv

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1
November 2014 SC '14: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis
Publisher: IEEE Press
Bibliometrics:
Citation Count: 7
Downloads (6 Weeks): 4,   Downloads (12 Months): 34,   Downloads (Overall): 310

Full text available: PDFPDF
Through-Silicon Interposer (TSI) has recently been proposed to provide high memory bandwidth and improve energy efficiency of the main memory system. However, the impact of TSI on main memory system architecture has not been well explored. While TSI improves the I/O energy efficiency, we show that it results in an ...

2
June 2014 ISCA '14: Proceeding of the 41st annual international symposium on Computer architecuture
Publisher: IEEE Press
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 6,   Downloads (12 Months): 71,   Downloads (Overall): 438

Full text available: PDFPDF
Modern DRAM devices for the main memory are structured to have multiple banks to satisfy ever-increasing throughput, energy-efficiency, and capacity demands. Due to tight cost constraints, only one row can be buffered (opened) per bank and actively service requests at a time, while the row must be deactivated (closed) before ...
Also published in:
October 2014  ACM SIGARCH Computer Architecture News - ISCA '14: Volume 42 Issue 3, June 2014

3
November 2013 ICCAD '13: Proceedings of the International Conference on Computer-Aided Design
Publisher: IEEE Press
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 0,   Downloads (12 Months): 5,   Downloads (Overall): 83

Full text available: PDFPDF
3D main memory is an emerging technology that stacks DRAM dies underneath the processor die using through-silicon vias (TSVs). Prior studies assumed that such technology would decrease main memory access latency by 45% to 60%, while also allowing designers to increase main memory bandwidth. Although the latter is true, it ...

4 published by ACM
September 2013 ACM Transactions on Architecture and Code Optimization (TACO): Volume 10 Issue 3, September 2013
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 5,   Downloads (12 Months): 47,   Downloads (Overall): 378

Full text available: PDFPDF
As the system size of supercomputers and datacenters increases, cost-efficient networks become critical in achieving good scalability on those systems. High -radix routers reduce network cost by lowering the network diameter while providing a high bisection bandwidth and path diversity. The building blocks of these large-scale networks are the routers ...
Keywords: Interconnection architectures, packet-switching networks, network topology

5 published by ACM
June 2013 ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture
Publisher: ACM
Bibliometrics:
Citation Count: 16
Downloads (6 Weeks): 11,   Downloads (12 Months): 161,   Downloads (Overall): 1,226

Full text available: PDFPDF
DRAM has been a de facto standard for main memory, and advances in process technology have led to a rapid increase in its capacity and bandwidth. In contrast, its random access latency has remained relatively stagnant, as it is still around 100 CPU clock cycles. Modern computer systems rely on ...
Keywords: DRAM, high-aspect-ratio mats, microarchitecture, asymmetric bank organizations
Also published in:
June 2013  ACM SIGARCH Computer Architecture News - ICSA '13: Volume 41 Issue 3, June 2013



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