ACM Transactions on Architecture and Code Optimization (TACO): Volume 11 Issue 1, February 2014
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Nonvolatile memories (NVMs) have the potential to replace low-level SRAM or eDRAM on-chip caches because NVMs save standby power and provide large cache capacity. However, limited write endurance is a common problem for NVM technologies, and today's cache management might result in unbalanced cache write traffic, causing heavily written cache ...
Cache, interset write variation, lifetime improvement, write endurance, wear leveling, intraset write variation