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 Eric Chung

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Average citations per article14.29
Citation Count100
Publication count7
Publication years2012-2019
Available for download2
Average downloads per article396.50
Downloads (cumulative)793
Downloads (12 Months)751
Downloads (6 Weeks)62
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1
May 2019 IEEE Micro: Volume 39 Issue 3, May 2019
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 0

Growing computational demands from deep neural networks (DNNs), coupled with diminishing returns from general-purpose architectures, have led to a proliferation of Neural Processing Units (NPUs). This paper describes the Project Brainwave NPU (BW-NPU), a parameterized microarchitecture specialized at synthesis time for convolutional and recurrent DNN workloads. The BW-NPU deployed on ...

2
June 2018 ISCA '18: Proceedings of the 45th Annual International Symposium on Computer Architecture
Publisher: IEEE Press
Bibliometrics:
Citation Count: 17
Downloads (6 Weeks): 55,   Downloads (12 Months): 562,   Downloads (Overall): 562

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Interactive AI-powered services require low-latency evaluation of deep neural network (DNN) models---aka "realtime AI". The growing demand for computationally expensive, state-of-the-art DNNs, coupled with diminishing performance gains of general-purpose architectures, has fueled an explosion of specialized Neural Processing Units (NPUs). NPUs for interactive services should satisfy two requirements: (1) execution ...
Keywords: accelerator architectures, field programmable gate arrays, neural network hardware

3
April 2018 NSDI'18: Proceedings of the 15th USENIX Conference on Networked Systems Design and Implementation
Publisher: USENIX Association
Bibliometrics:
Citation Count: 22

Modern cloud architectures rely on each server running its own networking stack to implement policies such as tunneling for virtual networks, security, and load balancing. However, these networking stacks are becoming increasingly complex as features are added and as network speeds increase. Running these stacks on CPU cores takes away ...

4
October 2016 MICRO-49: The 49th Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: IEEE Press
Bibliometrics:
Citation Count: 38
Downloads (6 Weeks): 7,   Downloads (12 Months): 189,   Downloads (Overall): 231

Full text available: PDFPDF
Hyperscale datacenter providers have struggled to balance the growing need for specialized hardware (efficiency) with the economic benefits of homogeneity (manageability). In this paper we propose a new cloud architecture that uses reconfigurable logic to accelerate both network plane functions and applications. This Configurable Cloud architecture places a layer of ...

5
May 2014 FCCM '14: Proceedings of the 2014 IEEE 22nd International Symposium on Field-Programmable Custom Computing Machines
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 5

Sparse matrix-vector multiplication (SMVM) is a crucial primitive used in a variety of scientific and commercial applications. Despite having significant parallelism, SMVM is a challenging kernel to optimize due to its irregular memory access characteristics. Numerous studies have proposed the use of FPGAs to accelerate SMVM implementations. However, most prior ...
Keywords: sparse matrix vector multiplication, FPGA, accelerator, SPMV, SMVM, reconfigurable computing, HPC

6
April 2012 FCCM '12: Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 7

We present the design and implementation of a universal, single-bit stream library for accelerating matrix-vector multiplication using FPGAs. Our library handles multiple matrix encodings ranging from dense to multiple sparse formats. A key novelty in our approach is the introduction of a hardware-optimized sparse matrix representation called Compressed Variable-Length Bit ...
Keywords: FPGA, dense matrix, sparse matrix, spMV, reconfigurable computing



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