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 Poovaiah M Palangappa

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Average citations per article2.60
Citation Count13
Publication count5
Publication years2014-2017
Available for download4
Average downloads per article102.75
Downloads (cumulative)411
Downloads (12 Months)209
Downloads (6 Weeks)59
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5 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
December 2017 ACM Transactions on Architecture and Code Optimization (TACO): Volume 14 Issue 4, December 2017
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 37,   Downloads (12 Months): 37,   Downloads (Overall): 37

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Emerging nonvolatile memories (NVMs) suffer from low write endurance, resulting in early cell failures (hard errors), which reduce memory lifetime. It was recognized early on that conventional error-correcting codes (ECCs), which are designed for soft errors, are a poor choice for addressing hard errors in NVMs. This led to the ...
Keywords: Nonvolatile memories, main memory, reliability

2 published by ACM
April 2017 ACM Transactions on Architecture and Code Optimization (TACO): Volume 14 Issue 1, April 2017
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 17,   Downloads (12 Months): 114,   Downloads (Overall): 114

Full text available: PDFPDF
Multilevel/triple-level cell nonvolatile memories (MLC/TLC NVMs) such as phase-change memory (PCM) and resistive RAM (RRAM) are the subject of active research and development as replacement candidates for DRAM, which is limited by its high refresh power and poor scaling potential. In addition to the benefits of nonvolatility (low refresh power) ...
Keywords: compression, energy, main memory, Nonvolatile memories, latency

3
April 2016 IEEE Transactions on Computers: Volume 65 Issue 4, April 2016
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 2

This paper describes a write-once-memory-code phase change memory (WOM-code PCM) architecture for next-generation non-volatile memory applications. Specifically, we address the long latency of the write operation in PCM—attributed to PCM SET—by proposing a novel PCM memory architecture that integrates the $\langle 2^2\rangle ^2/3$ WOM-code ...

4 published by ACM
May 2015 GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI
Publisher: ACM
Bibliometrics:
Citation Count: 6
Downloads (6 Weeks): 5,   Downloads (12 Months): 32,   Downloads (Overall): 182

Full text available: PDFPDF
This paper proposes Flip-Mirror-Rotate (FMR), an architecture for bit-write reduction and endurance enhancement in emerging non-volatile memories (NVMs). FMR comprises three components: adaptive Flip-N-Write (aFNW), Mirror-N-Write (MNW), and Rotate-N-Write (RNW). aFNW and MNW focus on word-level bit-write reduction, which reduces NVM dynamic energy while also improving endurance. RNW is an ...
Keywords: endurance, wear leveling, energy, non-volatile memory

5 published by ACM
July 2014 NANOARCH '14: Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures
Publisher: ACM
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 0,   Downloads (12 Months): 26,   Downloads (Overall): 78

Full text available: PDFPDF
This paper proposes a compression-based architecture for bit-write reduction in emerging non-volatile memories (NVMs). Bit-write reduction has many practical benefits, including lower write latency, lower dynamic energy, and enhanced endurance. The proposed architecture, which is integrated into the NVM module, relies on (i) a frequent pattern compression-decompression engine, (ii) a ...



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