ACM Transactions on Architecture and Code Optimization (TACO): Volume 12 Issue 4, January 2016
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Semiconductor device scaling has made single-ISA heterogeneous processors a reality. Heterogeneous processors contain a number of different CPU cores that all implement the same Instruction Set Architecture (ISA). This enables greater flexibility and specialization, as runtime constraints and workload characteristics can influence which core a given workload is run on. ...
effective speed, single-ISA, generality, set overhead, Localized nonuniformity, gap overhead