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Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination
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Authors:
Hsiang-Jen Tsai
Department of CS, National Chiao Tung University, Hsinchu, Taiwan, ROC
Chien-Chih Chen
Department of CS, National Chiao Tung University, Hsinchu, Taiwan, ROC
Keng-Hao Yang
Department of CS, National Chiao Tung University, Hsinchu, Taiwan, ROC
Ting-Chin Yang
Department of EE, National Tsing Hua University, Hsinchu, Taiwan, ROC
Li-Yue Huang
Department of EE, National Tsing Hua University, Hsinchu, Taiwan, ROC
Ching-Hao Chung
Department of EE, National Tsing Hua University, Hsinchu, Taiwan, ROC
Meng-Fan Chang
Department of EE, National Tsing Hua University, Hsinchu, Taiwan, ROC
Tien-Fu Chen
Department of CS, National Chiao Tung University, Hsinchu, Taiwan, ROC
2014 Article
Research
Refereed limited
Bibliometrics
· Citation Count: 3
· Downloads (cumulative): 192
· Downloads (12 Months): 5
· Downloads (6 Weeks): 0
Published in:
· Proceeding
DAC '14
Proceedings of the 51st Annual Design Automation Conference
Pages 1-6
San Francisco, CA, USA — June 01 - 05, 2014
ACM
New York, NY
, USA
©2014
table of contents
ISBN: 978-1-4503-2730-5
doi>
10.1145/2593069.2593153
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Author Tags
design
dynamic memory
emerging technologies
energy reduction
experimentation
management
memory structure
multi-core
non-volatile sram
nonvolatile memory
on-chip cache architecture
redundant store elimination
very large scale integration design
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