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In this article, we propose an FPGA-based SQL query processing approach exploiting the capabilities of partial dynamic reconfiguration of modern FPGAs. After the analysis of an incoming query, a query-specific hardware processing unit is generated on the fly and loaded on the FPGA for immediate query execution. For each query, a specialized hardware accelerator pipeline is composed and configured on the FPGA from a set of presynthesized hardware modules. These partially reconfigurable hardware modules are gathered in a library covering all major SQL operations like restrictions and aggregations, as well as more complex operations such as joins and sorts. Moreover, this holistic query processing approach in hardware supports different data processing strategies including row- as column-wise data processing in order to optimize data communication and processing. This article gives an overview of the proposed query processing methodology and the corresponding library of modules. Additionally, a performance analysis is introduced that is able to estimate the processing time of a query for different processing strategies and different communication and processing architecture configurations. With the help of this performance analysis, architectural bottlenecks may be exposed and future optimized architectures, besides the two prototypes presented here, may be determined.

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Author image not provided  Daniel Ziener

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Author image not provided  Florian Bauer

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Publication years2016-2016
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Author image not provided  Andreas Becher

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Publication years2016-2019
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Author image not provided  Christopher Dennl

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Publication years2012-2016
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Klaus Meyer-Wegener Klaus Meyer-Wegener

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Klaus.Meyer-Wegeneratfau.de
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Publication years1983-2016
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Author image not provided  Ute Schürfeld

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Publication years2016-2016
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Author image not provided  Jürgen Teich

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Author image not provided  Jörg-Stephan Vogt

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Author image not provided  Helmut Weber

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top of pageREFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Takashi Takenaka, Masamichi Takagi, and Hiroaki Inoue. 2012. A scalable complex event processing framework for combination of SQL-based continuous queries and C/C++ functions. In 22nd International Conference on Field Programmable Logic and Applications (FPL’12). 237--242. DOI:http://dx.doi.org/10.1109/FPL.2012.6339187
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Stefan Werner, Sven Groppe, Volker Linnemann, and Thilo Pionteck. 2013. Hardware-accelerated join processing in large semantic web databases with FPGAs. In International Conference on High Performance Computing and Simulation (HPCS’13). IEEE, 131--138.
 
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Xilinx. 2011. UG743: Overview of the Partial Reconfiguration Flow. Technical Report. Xilinx.

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The ACM Computing Classification System (CCS rev.2012)

Note: Larger/Darker text within each node indicates a higher relevance of the materials to the taxonomic classification.

top of pagePUBLICATION

Title ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Regular Papers and Special Section on Field Programmable Gate Arrays (FPGA) 2015 TRETS Homepage table of contents archive
Volume 9 Issue 4, September 2016
Editor Steve Wilton Department of Electrical and Computer Engineering/University of British Columbia/Kaiser 4112, 5500-2332 Main Mall/Vancouver, BC V6T 1Z4 Canada
Article No. 25
Publication Date2016-09-20 (yyyy-mm-dd)
PublisherACM New York, NY, USA
ISSN: 1936-7406 EISSN: 1936-7414 doi>10.1145/2845087

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top of pageTable of Contents

ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Regular Papers and Special Section on Field Programmable Gate Arrays (FPGA) 2015

Volume 9 Issue 4, September 2016

Table of Contents
SECTION: Regular Papers
A Retargetable Compilation Framework for Heterogeneous Reconfigurable Computing
Zain Ul-Abdin, Bertil Svensson
Article No.: 24
doi>10.1145/2843946
Full text: PDFPDF

The future trend in microprocessors for the more advanced embedded systems is focusing on massively parallel reconfigurable architectures, consisting of heterogeneous ensembles of hundreds of processing elements communicating over a reconfigurable interconnection ...
expand
FPGA-Based Dynamically Reconfigurable SQL Query Processing
Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt, Helmut Weber
Article No.: 25
doi>10.1145/2845087
Full text: PDFPDF

In this article, we propose an FPGA-based SQL query processing approach exploiting the capabilities of partial dynamic reconfiguration of modern FPGAs. After the analysis of an incoming query, a query-specific hardware processing unit is generated on ...
expand
Shared Memory Multicore MicroBlaze System with SMP Linux Support
Eric Matthews, Lesley Shannon, Alexandra Fedorova
Article No.: 26
doi>10.1145/2870638
Full text: PDFPDF

In this work, we present PolyBlaze, a scalable and configurable multicore platform for FPGA-based embedded systems and systems research. PolyBlaze is an extension of the MicroBlaze soft processor, leveraging the configurability of the MicroBlaze and ...
expand
ODoST: Automatic Hardware Acceleration for Biomedical Model Integration
Ting Yu, Chris Bradley, Oliver Sinnen
Article No.: 27
doi>10.1145/2870639
Full text: PDFPDF

Dynamic biomedical systems are mathematically described by Ordinary Differential Equations (ODEs) and their solution is often one of the most computationally intensive parts in biomedical simulations. With high inherent parallelism, hardware acceleration ...
expand
SECTION: Special Section on Field Programmable Gate Arrays (FPGA) 2015
Introduction
Deming Chen
Article No.: 28
doi>10.1145/2955103
Full text: PDFPDF
Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs
Evan Wegley, Yanhua Yi, Qinhai Zhang
Article No.: 29
doi>10.1145/2892640
Full text: PDFPDF

In addition to optimizing for long-path timing and routability, commercial FPGA routing engines must also optimize for various timing constraints, enabling users to fine tune their designs. These timing constraints involve both long- and short-path timing ...
expand
Impact of Parallelism and Memory Architecture on FPGA Communication Energy
Edin Kadric, David Lakata, André Dehon
Article No.: 30
doi>10.1145/2857057
Full text: PDFPDF

The energy in FPGA computations is dominated by data communication energy, either in the form of memory references or data movement on interconnect. In this article, we explore how to use data placement and parallelism to reduce communication energy. ...
expand
Fine-Grained Interconnect Synthesis
Alex Rodionov, David Biancolin, Jonathan Rose
Article No.: 31
doi>10.1145/2892641
Full text: PDFPDF

One of the key challenges for the FPGA industry going forward is to make the task of designing hardware easier. A significant portion of that design task is the creation of the interconnect pathways between functional structures. We present a synthesis ...
expand

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