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Hardware microcontrol schemes using PLAs

Published:01 December 1981Publication History
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Abstract

Four new schemes for microprogram control design with programmable logic arrays (PLAs) are proposed. The general structure of the first three schemes consists of three units namely, the microcode memory (ROM), the microsequencer PLA, and a register-counter. The basic idea is to store only branching information, by means of control constructs or transactions, in the PLA(s). These transactions have simple jump-type or continue-type formats with only the jump being embedded in PLA(s).

A more general structure, scheme 4, is also proposed with the objective to generate powerful transactions implementing complex control constructs, such as microsubroutines, nested microprogram loops, etc., in addition to multiway branch capability. These transactions contain horizontally formatted directive bits and, hence, they exhibit a measure of parrallelism. The aim is to transform the sequencing structure of a microprogram into a “program” composed of these transactions. However, a directive-driven processor is required to execute each transaction in order to produce the desired address.

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          • Published in

            cover image ACM SIGMICRO Newsletter
            ACM SIGMICRO Newsletter  Volume 12, Issue 4
            Dec. 1981
            187 pages
            ISSN:1050-916X
            DOI:10.1145/1014192
            Issue’s Table of Contents
            • cover image ACM Conferences
              MICRO 14: Proceedings of the 14th annual workshop on Microprogramming
              December 1981
              214 pages

            Copyright © 1981 Author

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            Association for Computing Machinery

            New York, NY, United States

            Publication History

            • Published: 1 December 1981

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