Abstract
The problem of reducing the microinstruction length for a parallel microprogram, by trading off microprogram width (bits) for subsequent logic, is considered. In a generalization of previous methods, it is shown that a considerable reduction of microprogram storage size can be achieved by selecting a subset of the original microorders to serve as inputs to some generating logic in order to provide all the microorders in the original microprogram. Heuristic solution methods are shown, along with ways to control the bounds of the solutions, allowing the designer the choice between a fast solution and an optimal solution. Examples show the effects of using these methods, alone and in conjunction with previously published methods for width reduction. Applications of the width reduction technique to reasonable modern design situations are discussed.
- 1 S. Davison, et. al., "Some experiments in local microcode compaction for horizontal machines," IEEE Trans., C-30, pp. 460-477, July 1981.Google Scholar
Digital Library
- 2 J. A. Fisher, "Trace scheduling: A technique for global microcode compaction," IEEE Trans., C-30, pp. 478-490, July 1981.Google Scholar
Digital Library
- 3 M. Tokoro, et. al., "Optimization of microprograms," IEEE Trans., C-30, pp. 491-504, July 1981.Google Scholar
Digital Library
- 4 S. Dasgupta, "The organization of microprogram stores," Computing Surveys, 11, 1, pp. 39-65, March 1979. Google Scholar
Digital Library
- 5 T. G. Rauscher, P. N. Adams, "Microprogramming: a tutorial and survey of recent developments," IEEE Trans, C-29, pp. 2-20, January 1980.Google Scholar
- 6 K. M. Guttag, "Compressing control ROM for VLSI microprogrammed microprocessors," 13th Annual Microprogramming Workshop, ACM SIGMICRO News-letter, 11, nos. 3 & 4, pp. 115-121, December 1980. Google Scholar
Digital Library
- 7 E. L. Robertson, "Microcode bit optimization is NP complete," IEEE Trans., C-28, 4, pp. 316-319, April 1979.Google Scholar
Digital Library
- 8 C. Halatsis, N. Gaitanis, "On the minimization of the control store in microprogrammed computers," IEEE Trans., C-27, 12, pp. 1189-1192, December 1978.Google Scholar
Digital Library
- 9 A. Grasselli and U. Montanari, "On the minimization of read only memories in microprogrammed digital computers," IEEE Trans., C-19, pp. 1111-1114, November 1970.Google Scholar
Digital Library
- 10 S. J. Schwartz, "An algorithm for minimizing read-only memories for machine control," in Proc. IEEE 9th Annual Symp. Switching and Automata Theory, pp. 28-33, 1968.Google Scholar
- 11 T. Jayasri and D. Basu, "An approach to organizing microinstructions which minimizes the width of control store words," IEEE Trans., C-25, pp. 514-521, May 1976.Google Scholar
Digital Library
- 12 J. L. Baer and B. Koyama, "On the minimization of the width of the control memory of microprogrammed processors," IEEE Trans., C-28, pp. 310-316, April 1979.Google Scholar
Digital Library
- 13 A. Mathialagan and N. N. Biswas, "Bit steering in the minimization of control memory in microprogrammed digital computers," IEEE Trans., C-30, pp. 144-147, February 1981.Google Scholar
Cross Ref
- 14 S. Stritter and N. Tredenick, "Microprogrammed implementation of a single chip microprocessor," Proc. 11th Annual Microprogramming Workshop, December 1978. Google Scholar
Digital Library
- 15 J. F. Martinez-Carballido and V. M. Powers, "Microprogram width reduction methods," Tech. Rept., Dept. of Elect. & Computer Engineering, Oregon State University, June 3, 1981.Google Scholar
- 16 M. Andrews, Principles of firmware engineering in microprogram control, Computer Science Press, 1980. Google Scholar
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Index Terms
General microprogram width reduction using generator sets
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General microprogram width reduction using generator sets
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