Abstract
This keynote address contains a brief account of the arguements being advanced in favor of reduced instruction sets. These arguements have relevance both to single chip computers and to larger computers. Some comments are made on instruction set design from a compiler writer's point of view, and on the advantages to be gained from regarding the design of an instruction set and the code generator of the compiler as a single task.
- 1 Hennessy, Jr., Jouppi, N., Baskett, F., Gross, T. and Gill, J. "Hardware/Software Tradeoffs for Increased Performance." Computer Architecture News 10,2 p 2; Sigplan Notices 17,4 p 2 (1982) Google Scholar
Digital Library
- 2 Patterson,D.A. and Ditzel, D.R. "The Case for the Reduced Instruction Set Computer." Computer Architecture News 9,3 p 25 (1980) Google Scholar
Digital Library
- 3 Patterson, D.A. and Sequin, C.H. "RISC 1: A Reduced Instruction Set VLSI Computer." Proc. 8th Symposium on Computer Architecture, Minneapolis, Minn. p 443 (1981) Google Scholar
Digital Library
- 4 Radin, G. "The 801 Minicomputer." Computer Architecture News 10,2 p 39; Sigplan Notices 17,4 p 39 (1982) Google Scholar
Digital Library
- 5 Sweet, R. and Sandman, J. "Static Analysis of the Mesa Instruction Set." Computer Architecture News 10,2 p 158; Sigplan Notices 17,4 p 158 (1982) Google Scholar
Digital Library
- 6 Wirth, N. "The Personal Computer LILITH" Instut fur Informatik, ETH, Zurich, Report # 40 (1981)Google Scholar
- 7 Wulf, W.A. "Compilers and Computer Architecture." Computer 14,7 p 41 (1981)Google Scholar
Index Terms
Keynote address - the processor instruction set
Recommendations
Keynote address - the processor instruction set
MICRO 15: Proceedings of the 15th annual workshop on MicroprogrammingThis keynote address contains a brief account of the arguements being advanced in favor of reduced instruction sets. These arguements have relevance both to single chip computers and to larger computers. Some comments are made on instruction set design ...
Automatic custom instruction identification for application-specific instruction set processors
The application-specific instruction set processors (ASIPs) have received more and more attention in recent years. ASIPs make trade-offs between flexibility and performance by extending the base instruction set of a general-purpose processor with custom ...
Selection of instruction set extensions for an FPGA embedded processor core
IPDPS'06: Proceedings of the 20th international conference on Parallel and distributed processingA design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The instruction set of the PowerPC 405 is extended by selecting additional ...






Comments