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Nanosecond threshold logic gates for 16 X 16 bit, 80 ns LSI multiplier
AFIPS '69 (Fall): Proceedings of the November 18-20, 1969, fall joint computer conferencePrevious research and development efforts in digital monolithic integrated circuits and arrays were almost exclusively concerned with Boolean logic. However, by introducing threshold logic, considerable savings in gate count as well as in subsystem ...
A Layout System for the Random Logic Portion of an MOS LSI Chip
The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multiphase clocking system, and occupies ordinarily a considerable part of ...






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