A highly efficient AES cipher chip

ABSTRACT

We present an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Instead of the widely used table-lookup implementation of S-box, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64% and is easily pipelined to achieve high throughput rate. Using a typical 0.25μm CMOS technology, the throughput rate is 2.977 Gbps for 128-bit keys, 2.510 Gbps for 192-bit keys, and 2.169 Gbps for 256-bit keys with a 250MHz clock. Testability of the design is also considered. The area of the core circuit is about 1,279 x 1,271μm².

References

1. National Institute of Standards and Technology (NIST), Advanced Encryption Standard (AES), National Technical Information Service, Springfield, VA 22161, Nov. 2001.]]
2. A. J. Elbirt, W. Yip, B. Chetwynd, and C. Paar, "An FPGA-Based performance evaluation of the AES block cipher candidate algorithm finalists", IEEE Trans. VLSI Systems, vol. 9, no. 4, pp. 545--557, Aug. 2001.]]
3. H. Kuo and I. Verbauwhede, "Architectural optimization for a 1.82 Gbits/sec VLSI implementation of the AES Rijndael algorithm", in Cryptographic Hardware and Embedded Systems (CHES) 2001, Ç. K. Koç, D. Naccache, and C. Paar, Eds. 2001, number 2162 in LNCS, Springer-Verlag.]]
4. T.-F. Lin, C.-P. Su, C.-T. Huang, and C.-W. Wu, "A high-throughput low-cost AES cipher chip", in Proc. 3rd IEEE Asia-Pacific Conf. ASIC, Taipei, Aug. 2002, pp. 85--88.]]

Index Terms

• Hardware

  • Hardware validation

  • Very large scale integration design

    • Application-specific VLSI designs

      • Application specific processors

• Information systems

  • Data management systems

    • Data structures

      • Data layout

        • Data encryption

• Security and privacy

  • Cryptography