John Oliver
ABSTRACT
In this paper, we investigate the power implications of tile size selection for tile-based processors. We refer to this investigation as a tile granularity study. This is accomplished by distilling the architectural cost of tiles with different computational widths into a system metric we call the Granularity Indicator (GI). The GI is then compared against the communications exposed when algorithms are partitioned across multiple tiles. Through this comparison, the tile granularity that best fits a given set of algorithms can be determined, reducing the system power for that set of algorithms. When the GI analysis is applied to the Synchroscalar tile architecture[1], we find that Synchroscalar's already low power consumption can be further reduced by 14% when customized for execution of the 802.11a reciever. In addition, the GI can also be a used to evaluate tile size when considering multiple applications simultaneously, providing a convenient platform for hardware-software co-design.
- J. Oliver, R. Rao, P. Sultatna, J. Crandall, E. Czernikowski, L. W. Jones, D. Franklin, V. Akella, and F. T. Chong, Synchroscalar: A multiple clock domain, power-aware, tile-based embedded processor," in 31th Annual International Symposium on Computer Architecture (31th ISCA-2004) Computer Architecture News, ACM SIGARCH/IEEE, June 2004. Google Scholar
Digital Library
- M. B. Taylor et al., The Raw microprocessor: A computational fabric for software circuits and general-purpose programs," IEEE Micro, vol. 22, pp. 25--35, Mar.Apr. 2002. Google ScholarDigital Library
- K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, N. Ranganathan, D. Burger, S. W. Keckler, R. G. McDonald, and C. R. Moore, Trips: A polymorphous architecture for exploiting ilp, tlp, and dlp," ACM Trans. Archit. Code Optim., vol. 1, no. 1, pp. 62--93, 2004. Google ScholarDigital Library
- K. Mai, T. Paaske, N. Jayasena, R. Ho, W. J. Dally, and M. Horowitz, Smart memories: A modular recongurable architecture," in 27th Annual International Symposium on Computer Architecture (27th ISCA-2000) Computer Architecture News, (Vancouver, British Columbia, Canada), ACM SIGARCH / IEEE, June 2000. Published as 27th Annual International Symposium on Computer Architecture (27th ISCA-2000) Computer Architecture News, volume 28. Google ScholarDigital Library
- M. B. Taylor, W. Lee, J. Miller, D. Wentzla, I. Bratt, B. Greenwald, H. Hoffmann, P. Johnson, J. Kim, J. Psota, A. Saraf, N. Shnidman, V. Strumpen, M. Frank, S. P. Amarasinghe, and A. Agarwal, Evaluation of the raw microprocessor: An exposed-wire-delay architecture for ilp and streams.," in ISCA, pp. 2--13, 2004. Google ScholarDigital Library
- R. Kolagotla, J. Fridman, B. Aldrich, M. Hoffman, W. Anderson, M. Allen, D. Witt, R. Dunton, and L. Booth, High Performance Dual-MAC DSP Architecture," IEEE Signal Processing Magazine, July 2002.Google Scholar
- S. Gupta, S. Keckler, and D. Burger, Technology independent area and delay estimates for microprocessor building blocks," in Technical Report TR2000-05, Department of Computer Science, University of Texas, 2000. Google ScholarDigital Library
- A. Wolfe, J. Fritts, S. Dutta, and E. S. T. Fernandes, Datapath design for a vliw video signal processor.," in HPCA, pp. 24-, 1997. Google ScholarDigital Library
- S. Rixner, W. Dally, B. Khailany, P. Mattson, U. Kapasi, and J. Owens, Register Organization for Media Processing," in International Symposium on High Performance Computer Architecture (HPCA), (Toulouse, France), January 2000.Google Scholar
- S. Thompson, M. Alavi, M. Hussein, P. Jacob, C. Kenyon, P. Moon, M. Prince, S. Sivakumar, S. Tyagi, and M. Bohr, 130nm logic technology featuring 60nm transistors, low-k dielectrics, and cu interconnects," Intel Technology Journal, vol. 6, pp. 5--13, May 2002.Google Scholar
- ADSP-2191 Processor Data Sheet." 2002.Google Scholar
- TMS320C28x Processor Manual." July 2001.Google Scholar
- M. Y. T. Kumura, M. Ikekawa and I. Kuroda, VLIW DSP for Mobile Applications," IEEE Signal Processing Magazine, July 2002.Google Scholar
- H. Mizuno, N. Irie, K. Uchiyama, Y. Yanagisawa, S. Yoshioka, I. Kawasaki, and T. Hattori, SH-Mobile3: Application Processor for 3G Cellular Phones on a Low-Power SoC Design Platform," Hot Chips 16, August 2004.Google Scholar
- E. Norden, P. Leteinturier, J. Barrenscheen, K. Scheibert, and F. Hellwig, A Fast Powertrain Microcontroller," August 2004.Google Scholar
- TS-101 Data Sheet." August 2002.Google Scholar
- Transmeta Crusoe TM5700/5900 Processors." 2003.Google Scholar
- Transmeta Crusoe TM8300/8600 Processors." 2004.Google Scholar
- TMS320C62x Processor Manual." July 2001.Google Scholar
- S. A. et. al., A 600MHz VLIW DSP," February 2002.Google Scholar
- TMS320DM642 Data Sheet." 2005.Google Scholar
- U. SMART Interconnect Group, Flexsim 1.2 it level simulator." http://ceng.usc.edu/smart/tools.html.Google Scholar
- X. Chen and L.-S. Peh, Leakage power modeling and optimization in interconnection networks," in ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design, pp. 90--95, ACM Press, 2003. Google ScholarDigital Library
- R. Ho, K. Mai, and M. Horowitz, Efficient on-chip global interconnects," in IEEE Symposium on VLSI Circuits, June 2003. Stanford Univeristy.Google Scholar
- J. S. Kim, M. B. Taylor, J. Miller, and D. Wentzla, Energy characterization of a tiled architecture processor with on-chip networks," in ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design, pp. 424--427, ACM Press, 2003. Google ScholarDigital Library
- B. Hendrickson and R. Leland, The chaco user's guide, version 2.0, technical report sand94-2692," 1994. http://www.ti.com/corp/docs/press/backgrounder/omap.shtml.Google Scholar
- R. Krashinsky, C. Batten, M. Hampton, S. Gerding, B. Pharris, J. Casper, and K. Asanovic, The vector-thread architecture," SIGARCH Comput. Archit. News, vol. 32, no. 2, p. 52, 2004. Google ScholarDigital Library
- D. Marculescu, Application adaptive energy efficient clustered architectures," in ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design, pp. 344349, ACM Press, 2004. Google ScholarDigital Library
- V. Zyuban, Unifed architecture level energy-efficiency metric," in GLSVLSI '02: Proceedings of the 12th ACM Great Lakes symposium on VLSI, pp. 24--29, ACM Press, 2002. Google ScholarDigital Library
- A. Hartstein and T. R. Puzak, The optimum pipeline depth considering both power and performance," ACM Trans. Archit. Code Optim., vol. 1, no. 4, pp. 369--388, 2004. Google ScholarDigital Library
- J. A. Fisher, P. Faraboschi, and G. Desoli, Custom-fit processors: letting applications define architectures," in MICRO 29: Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, pp. 324--335, IEEE Computer Society, 1996. Google ScholarDigital Library
- S. Heo and K. Asanovic;, Replacing global wires with an on-chip network: a power analysis," in ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design, (New York, NY, USA), pp. 369--374, ACM Press, 2005. Google ScholarDigital Library
- M. Taylor, J. Kim, J. Miller, D. Wentzla, F. Ghodrat, B. Greenwald, H. Ho, m Lee, P. Johnson, W. Lee, A. Ma, A. Saraf, M. Seneski, N. Shnidman, V. Frank, S. Amarasinghe, and A. Agarwal, The raw microprocessor: A computational fabric for software circuits and general purpose programs," 2002.Google Scholar
- T. Y. Morad, U. C. Weiser, A. Kolodny, M. Valero, and E. Ayguade, Performance, power effociency and scalability fo asymmetric cluster chip multiprocessors," in CCIT Technical Report 514, Technion, 2005.Google Scholar
Index Terms
Tile size selection for low-power tile-based architectures
Recommendations
Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture
This paper investigates the impact of proper tile size selection on the power the power consumption for tile-based processors. We refer to this investigation as a tile <em>granularity</em>study. This is accomplished by distilling the architectural cost ...
The effect of malformed tiles on tile assemblies within the kinetic tile assembly model
Many different constructions of proofreading tile sets have been proposed in the literature to reduce the effect of deviations from ideal behaviour of the dynamics of the molecular tile self-assembly process. In this paper, we consider the effect on the ...
An introduction to tile-based self-assembly
In this tutorial, we give a brief introduction to the field of tile-based algorithmic self-assembly. We begin with a description of Winfree's abstract Tile Assembly Model (aTAM) and a few basic exercises in designing tile assembly systems. We then ...
Comments