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A global progressive register allocator

Published:11 June 2006Publication History
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Abstract

This paper describes a global progressive register allocator, a register allocator that uses an expressive model of the register allocation problem to quickly find a good allocation and then progressively find better allocations until a provably optimal solution is found or a preset time limit is reached. The key contributions of this paper are an expressive model of global register allocation based on multicommodity network flows that explicitly represents spill code optimization, register preferences, copy insertion, and constant rematerialization; two fast, but effective, heuristic allocators based on this model; and a more elaborate progressive allocator that uses Lagrangian relaxation to compute the optimality of its allocations. Our progressive allocator demonstrates code size improvements as large as 16.75% compared to a traditional graph allocator. On average, we observe an initial improvement of 3.47%, which increases progressively to 6.84% as more time is permitted for compilation.

References

  1. R. K. Ahuja, T. L. Magnanti, and J. B. Orlin. Network Flows: Theory, Algorithms, and Applications. Prentice-Hall, Inc., 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. A.W. Appel and L. George. Optimal spilling for CISC machines with few registers. In Proc. of the ACM/SIGPLAN Conf. on Prog. Lang. Design and Impl., pp. 243--253. ACM Press, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. B. M. Baker and J. Sheasby. Accelerating the convergence of subgradient optimisation. European Journal of Operational Research, 117(1):136--144, August 1999.Google ScholarGoogle ScholarCross RefCross Ref
  4. L. A. Belady. A study of replacement algorithms for virtual-storage computer. IBM Systems Journal, 5(2):78--101, 1966.Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. P. Bergner, P. Dahl, D. Engebretsen, and M. T. O'Keefe. Spill code minimization via interference region spilling. In ACM/SIGPLAN Conf. on Prog. Lang. Design and Impl., pp. 287--295, 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. D. Bernstein, M. Golumbic, Y. Mansour, R. Pinter, D. Goldin, H. Krawczyk, and I. Nahshon. Spill code minimization techniques for optimizing compilers. In Proc. of the ACM/SIGPLAN Conf. on Prog. Lang. Design and Impl., pp. 258--263. ACM Press, 1989. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. H. Bodlaender, J. Gustedt, and J. A. Telle. Linear-time register allocation for a fixed number of registers. In Proc. of the ACMSIAM Symposium on Discrete Algorithms, pp. 574--583. Society for Industrial and Applied Mathematics, 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. P. Briggs. Register allocation via graph coloring. PhD thesis, Rice University, Houston, TX, USA, 1992. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. P. Briggs, K. D. Cooper, and L. Torczon. Coloring register pairs. ACM Lett. Program. Lang. Syst., 1(1):3--13, 1992. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. P. Briggs, K. D. Cooper, and L. Torczon. Improvements to graph coloring register allocation. ACM Trans. Program. Lang. Syst., 16(3):428--455, 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. D. Callahan and B. Koblenz. Register allocation via hierarchical graph coloring. In Proc. of theACM/SIGPLAN Conf. on Prog. Lang. Design and Impl., pp. 192--203. ACM Press, 1991. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. G. J. Chaitin. Register allocation & spilling via graph coloring. In Proc. of the SIGPLAN symposium on Compiler Construction, pp. 98--101. ACM Press, 1982. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. F. Chow and J. Hennessy. Register allocation by priority-based coloring. In Proc. of the SIGPLAN symposium on Compiler Construction, pp. 222--232, 1984. ACM Press. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. K. Cooper, A. Dasgupta, and J. Eckhardt. Revisiting graph coloring register allocation: A study of the Chaitin-Briggs and Callahan-Koblenz algorithms. In Proc. of the Workshop on Languages and Compilers for Parallel Computing (LCPC'05), October 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. K. D. Cooper and L. T. Simpson. Live range splitting in a graph coloring register allocator. In Proc. of the 1998 Intl. Compiler Construction Conference, 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. M. Farach and V. Liberatore. On local register allocation. In Proc. of the ACM-SIAM Symposium on Discrete Algorithms, 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. C. Fu, K.Wilken, and D. Goodwin. A faster optimal register allocator. The Journal of Instruction-Level Parallelism, 7:1--31, January 2005.Google ScholarGoogle Scholar
  18. C. H. Gebotys. Low energy memory and register allocation using network flow. In Proc. of the 34th conference on Design Automation, pp. 435--440. ACM Press, 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. L. George and A. W. Appel. Iterated register coalescing. ACM Trans. Program. Lang. Syst., 18(3):300--324, 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. U. Hirnschrott, A. Krall, and B. Scholz. Graph coloring vs. optimal register allocation for optimizing compilers. In JMLC, pp. 202--213, 2003.Google ScholarGoogle ScholarCross RefCross Ref
  21. W. Hsu, C. N. Fisher, and J. R. Goodman. On the minimization of loads/stores in local register allocation. IEEE Trans. Softw. Eng., 15(10):1252--1260, 1989. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. ILOG CPLEX. http://www.ilog.com/products/cplex.Google ScholarGoogle Scholar
  23. K. Kennedy. Design and optimization of compilers, Index register allocation in straight line code and simple loops, pp. 51--63. Prentice- Hall, 1972.Google ScholarGoogle Scholar
  24. D. Koes and S. C. Goldstein. A progressive register allocator for irregular architectures. In Proc. of the Intl. Symposium on Code Generation and Optimization, pp. 269--280, Washington, DC, 2005. IEEE Computer Society. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. D. Koes and S. C. Goldstein. An analysis of graph coloring register allocation. Technical Report CMU-CS-06-111, Carnegie Mellon University, March 2006.Google ScholarGoogle Scholar
  26. D. J. Kolson, A. Nicolau, N. Dutt, and K. Kennedy. Optimal register assignment to loops for embedded code generation. ACM Transactions on Design Automation of Electronic Systems., 1(2):251--279, 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. T. Kong and K. D. Wilken. Precise register allocation for irregular architectures. In Proc. of the ACM/IEEE Intl. Symposium on Microarchitecture, pp. 297--307. IEEE Computer Society Press, 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. A. Koseki, H. Komatsu, and T. Nakatani. Preference-directed graph coloring. SIGPLAN Not., 37(5):33--44, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. C. Lemaréchal. Computational Combinatorial Optimization: Optimal or Provably Near-Optimal Solutions, volume 2241 of Lecture Notes in Computer Science, chapter Lagrangian Relaxation, pp. 112--156. Springer-Verlag Heidelberg, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. V. Liberatore, M. Farach-Colton, and U. Kremer. Evaluation of algorithms for local register allocation. In Proc. of the Intl. Compiler Construction Conference, volume 1575 of Lecture Notes in Computer Science. Springer, 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. F. Luccio. A comment on index register allocation. Commun. ACM, 10(9):572--574, 1967. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. G. Lueh, T. Gross, and A. Adl-Tabatabai. Fusion-based register allocation. ACM Trans. Program. Lang. Syst., 22(3):431--470, 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. A. R. Madabushi. Lagrangian relaxation / dual approaches for solving large-scale linear programming problems. Master's thesis, Virginia Polytechnic Institute and State University, February 1997.Google ScholarGoogle Scholar
  34. W. M. Meleis and E. S. Davidson. Optimal local register allocation for a multiple-issue machine. In Proc. of the 8th Intl. Conf. on Supercomputing, pp. 107--116. ACM Press, 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. R. Motwani, K. V. Palem, V. Sarkar, and S. Reyen. Combining register allocation and instruction scheduling. Technical report, Stanford University, Stanford, CA, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. M. Naik and J. Palsberg. Compiling with code-size constraints. In Proc. of the conference on Languages, Compilers and Tools for Embedded Systems, pp. 120--129. ACM Press, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. M. Ogawa, Z. Hu, and I. Sasano. Iterative-free program analysis. In Proc. of Intl. Conference on Functional Programming, pp. 111--123. ACM Press, 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  38. M. Poletto and V. Sarkar. Linear scan register allocation. ACM Trans. Program. Lang. Syst., 21(5):895--913, 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  39. J. Ruttenberg, G. R. Gao, A. Stoutchinin, and W. Lichtenstein. Software pipelining showdown: optimal vs. heuristic methods in a production compiler. In Proc. of ACM/SIGPLAN Conf. on Prog. Lang. Design and Impl., pp. 1--11, 1996. ACM Press. Google ScholarGoogle ScholarDigital LibraryDigital Library
  40. M. D. Smith, N. Ramsey, and G. Holloway. A generalized algorithm for graph-coloring register allocation. SIGPLAN Not., 39(6):277--288, 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  41. M. Thorup. All structured programs have small tree width and good register allocation. Inf. Comput., 142(2):159--181, 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  42. O. Traub, G. Holloway, and M. D. Smith. Quality and speed in linear-scan register allocation. In Proc. of the ACM/SIGPLAN Conf. on Prog. Lang. Design and Impl., pp. 142--151, 1998. ACM Press. Google ScholarGoogle ScholarDigital LibraryDigital Library
  43. C. Wimmer and H. Mössenböck. Optimized interval splitting in a linear scan register allocator. In Proc. of ACM/USENIX Intl. Conf. on Virtual Execution Environments, pp. 132--141, 2005. ACM Press. Google ScholarGoogle ScholarDigital LibraryDigital Library

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    • Published in

      cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 41, Issue 6
      Proceedings of the 2006 PLDI Conference
      June 2006
      426 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/1133255
      Issue’s Table of Contents
      • cover image ACM Conferences
        PLDI '06: Proceedings of the 27th ACM SIGPLAN Conference on Programming Language Design and Implementation
        June 2006
        438 pages
        ISBN:1595933204
        DOI:10.1145/1133981

      Copyright © 2006 ACM

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      • Published: 11 June 2006

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