Abstract
In order to generate high-quality code for modern processors, a compiler must aggressively schedule instructions, maximizing resource utilization for execution efficiency. For a compiler to produce such code, it must avoid structural hazards by being aware of the processor's available resources and of how these resources are utilized by each instruction. Unfortunately, the most prevalent approach to constructing such a scheduler, manually discovering and specifying this information, is both tedious and error-prone. This paper presents a new approach which, when given a processor or processor model, automatically determines this information. After establishing that the problem of perfectly determining a processor's structural hazards through probing is not solvable, this paper proposes a heuristic algorithm that discovers most of this information in practice. This can be used either to alleviate the problems associated with manual creation or to verify an existing specification. Scheduling with these automatically derived structural hazards yields almost all of the performance gain achieved using perfect hazard information.
- BAKER, H. G. Precise instruction scheduling without a precise machine model. ACM SIGARCH Computer Architecture News 19, 6 (1991). Google Scholar
Digital Library
- BALA, V., AND RUBIN, N. Efficient instruction scheduling using finite state automata. In Proceedings of the 28th annual international symposium on Microarchitecture (1995). Google Scholar
Digital Library
- BRADLEE, D. G., HENRY, R. R., AND EGGERS, S. J. The Marion system for retargetable instruction scheduling. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (June 1991), pp. 229--240. Google Scholar
Digital Library
- CHANG, P. P.,MAHLKE, S. A., CHEN, W. Y.,WARTER, N. J., AND HWU, W. W. IMPACT: An architectural framework for multipleinstruction-issue processors. In Proceedings of the 18th International Symposium on Computer Architecture (May 1991), pp. 266--275. Google Scholar
Digital Library
- COLLARD, J.-F., AND LAVERY, D. Optimizations to prevent cache penalties for the Intel Itanium 2 processor. In Proceedings of the International Symposium on Code Generation and Optimization (2003), IEEE Computer Society, pp. 105--114. Google Scholar
Digital Library
- COLLBERG, C. S. Automatic derivation of compiler machine descriptions. Proceedings of the 2002 ACM Transactions on Programming Languages and Systems 24, 4 (2002). Google Scholar
Digital Library
- DAVIDSON, E. S., SHAR, L. E., THOMAS, A. T., AND PATEL, J. H. Effective control for pipelined computers. In Proceedings of the IEEE Spring Compcon 75 (February 1975), pp. 181--184.Google Scholar
- DEHNERT, J. C., AND TOWLE, R. A. Compiling for the Cydra 5. The Journal of Supercomputing 7, 1 (January 1993), 181--227. Google Scholar
Digital Library
- DUPRÈ, M., DRANCH, N., AND TEMAM, O. VHC: Quickly building an optimizer for complex embedded architectures. In Proceedings of the International Symposium on Code Generation and Optimization (2004), IEEE Computer Society. Google Scholar
Digital Library
- EICHENBERGER, A. E., AND DAVIDSON, E. S. A reduced multipipeline machine description that preserves scheduling constraints. In Proceedings of the ACM SIGPLAN '96 Conference on Programming Language Design and Implementation (May 1996), pp. 12--20. Google Scholar
Digital Library
- ENGBLOM, J. Processor Pipelines and Static Worst-Case Execution Time Analysis. PhD thesis, Department of Information Technology, Uppsala University, Sweden, March 2002.Google Scholar
- ENGLER, D. R., AND HSIEH, W. C. Derive: A tool that automatically reverse engineers instruction encodings. In Proceedings of the ACM SIGPLAN Workshop on Dynamic and Adaptive Compilation and Optimization (2000). Google Scholar
Digital Library
- ERANIAN, S. Perfmon: Linux performance monitoring for IA-64. http://www.hpl.hp.com/research/linux/perfmon/, 2003.Google Scholar
- ERANIAN, S. Perfmon: Linux performance monitoring for IA-64. http://www.hpl.hp.com/research/linux/perfmon/, 2003.Google Scholar
- FISHER, J. A. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers C-30, 7 (July 1981), 478--490.Google Scholar
Digital Library
- GRUN, P., HALAMBI, A., DUTT, N., AND NICOLAU, A. RTGEN: An algorithm for automatic generation of reservation tables from architectural descriptions. IEEE Transactions on Very Large Scale Integration Systems 11, 4 (2003), 731--737. Google Scholar
Digital Library
- GYLLENHAAL, J. C., HWU, W.W., AND RAU, B. R. Optimization of machine descriptions for efficient use. In Proceedings of the 29th International Symposium on Microarchitecture (December 1996), pp. 349--358. Google Scholar
Digital Library
- HANONO, S., AND DEVADAS, S. Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator. In Proceedings of the 35th Design Automation Conference (June 1998). Google Scholar
Digital Library
- HENNESSY, J. L., AND GROSS, T. Postpass code optimization of pipeline constraints. ACM Trans. on Programming Languages and Systems 5 (July 1983), 422--448. Google Scholar
Digital Library
- IMPACT. Personal Communication, IMPACT Research Group, March 2004.Google Scholar
- INTEL CORPORATION. Introduction to Microarchitectural Optimzation for Itanium 2 Processors: Reference Manual. Santa Clara, CA, 2002.Google Scholar
- INTEL CORPORATION. Intel Itanium 2 Processor Reference Manual: For Software Development and Optimization. Santa Clara, CA, April 2003.Google Scholar
- KÄSTNER, D. TDL: A hardware description language for retargetable postpass optimizations and analyses. In Proceedings of the Second International Conference on Generative Programming and Component Engineering (2003), pp. 18--36. Google Scholar
Digital Library
- KNUTH, D. E. The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms. Addison-Wesley Longman Publishing Co., Inc., 1997. Google Scholar
Digital Library
- LAM, M. S. Software pipelining: An effective scheduling technique for VLIW machines. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (June 1988), pp. 318--328. Google Scholar
Digital Library
- MILNER, C. W., AND DAVIDSON, J. W. Quick piping: a fast, highlevel model for describing processor pipelines. In LCTES/SCOPES'02: Proceedings of the Joint Conference on Languages, Compilers and Tools for Embedded Systems (2002), pp. 175--184. Google Scholar
Digital Library
- MISHRA, P., DUTT, N., AND NICOLAU, A. Functional abstraction driven design space exploration of heterogeneous programmable architectures. In Proceedings of the International Symposium on System Synthesis (October 2001), pp. 256--261. Google Scholar
Digital Library
- OPENIMPACT. Web site: http://gelato.uiuc.edu.Google Scholar
- PARENT, J. Detecting instruction scheduling constraints, May 2003. Senior Thesis, Department of Computer Science, Hamilton College.Google Scholar
- PROEBSTING, T. A., AND FRASER, C. W. Detecting pipeline structural hazards quickly. In Proceedings of the ACM Symposium on Principles of Programming Languages (January 1994), pp. 280--286. Google Scholar
Digital Library
- RAJAGOPALAN, S., VACHHARAJANI, M., AND MALIK, S. Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES) (November 2000), pp. 157--164. Google Scholar
Digital Library
- RAMSEY, N., AND DAVIDSON, J. Machine descriptions to build tools for embedded systems. In Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, Lecture Notes in Computer Science (June 1998), vol. 1474, pp. 172--188. Google Scholar
Digital Library
- SUGA, A., AND MATSUNAMI, K. Introducing the FR500 embedded microprocessor. IEEE Micro 20 (July 2000), 21--27. Google Scholar
Digital Library
- WAHLEN, O., HOHENAUER, M., LEUPERS, R., AND MEYR, H. Instruction scheduler generation for retargetable compilation. Design & Test of Computers, IEEE 20, 1 (January 2003), 34--41. Google Scholar
Digital Library
- YOTOV, K., PINGALI, K., AND STODGHILL, P. X-ray: A tool for automatic measurement of hardware parameters. In Proceedings of the 2nd International Conference on Quantitative Evaluation of SysTems (2005). Google Scholar
Digital Library
- ZIMMERMAN, G. The MIMOLA design system: A computer aided processor design method. In Proceedings of the 16th Annual Design Automation Conference (1979), pp. 53--58. Google Scholar
Digital Library
- ŽIVOJNOVIĆ, V., PEES, S., AND MEYR, H. LISA - machine description language and generic machine model for HW/SW codesign. In Proceedings of the IEEE Workshop on VLSI Signal Processing (San Francisco, CA, October 1996).Google Scholar
Cross Ref
Index Terms
Automatic instruction scheduler retargeting by reverse-engineering
Recommendations
Automatic instruction scheduler retargeting by reverse-engineering
PLDI '06: Proceedings of the 27th ACM SIGPLAN Conference on Programming Language Design and ImplementationIn order to generate high-quality code for modern processors, a compiler must aggressively schedule instructions, maximizing resource utilization for execution efficiency. For a compiler to produce such code, it must avoid structural hazards by being ...
Fast, frequency-based, integrated register allocation and instruction scheduling
Instruction scheduling and register allocation are two of the most important optimization phases in modern compilers as they have a significant impact on the quality of the generated code. Unfortunately, the objectives of these two optimizations are in ...







Comments