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Reducing NoC energy consumption through compiler-directed channel voltage scaling

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Published:11 June 2006Publication History

ABSTRACT

While scalable NoC (Network-on-Chip) based communication architectures have clear advantages over long point-to-point communication channels, their power consumption can be very high. In contrast to most of the existing hardware-based efforts on NoC power optimization, this paper proposes a compiler-directed approach where the compiler decides the appropriate voltage/frequency levels to be used for each communication channel in the NoC. Our approach builds and operates on a novel graph based representation of a parallel program and has been implemented within an optimizing compiler and tested using 12 embedded benchmarks. Our experiments indicate that the proposed approach behaves better - from both performance and power perspectives - than a hardwarebased scheme and the energy savings it achieves are very close to the savings that could be obtained from an optimal, but hypothetical voltage/frequency scaling scheme.

References

  1. Mediabench. http://cares.icsl.ucla.edu/MediaBench/.Google ScholarGoogle Scholar
  2. Mibench. http://www.eecs.umich.edu/mibench.Google ScholarGoogle Scholar
  3. Virtutech simics. http://www.virtutech.com/products/.Google ScholarGoogle Scholar
  4. R. K. Barua. Maps: A Compiler-Managed Memory System for Raw Machines. PhD thesis, Massachusetts Institute of Technology, Cambridge, MA, USA, 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. L. Benini and G. D. Micheli. Networks on chips: a new SoC paradigm. IEEE Computer, 35(1):70--78, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In Proc. the International Symposium on Computer Architecture, pages 83--94, 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. G. Chen, F. Li, and M. Kandemir. Compiler-directed channel allocation for saving power in on-chip networks. In Proc. Symposium on Principles of Programming Languages, Charleston, SC, Jan. 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. K. D. Cooper, K. Kennedy, and N. McIntosh. Cross-loop reuse analysis and its application to cache optimizations. In Proc. Workshop on Languages and Compilers for Parallel Computing, 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. W. J. Dally and B. Towles. Route packets, not wires: on-chip inteconnectoin networks. In Proc. the 38th Conference on Design Automation, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. N. Eisley and L.-S. Peh. High-level power analysis of on-chip networks. In Proc. the 7th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Sept. 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. J. Hu and R. Marculescu. Energy- and performance-aware mapping for regular noc architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(4), April 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. E. J. Kim, K. H. Yum, G. Link, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, M. Yousif, and C. R. Das. Energy optimization techniques in cluster interconnects. In Proc. the International Symposium on Low Power Electronics and Design, Aug. 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. I. Kolcu. Personal communication.Google ScholarGoogle Scholar
  14. W. Lee, D. Puppin, S. Swenson, and S. Amarasinghe. Convergent scheduling. In Proc. the 35th International Symposium on Microarchitecture, Nov. 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. F. Li, G. Chen, and M. Kandemir. Compiler-directed voltage scaling on communication links for reducing power consumption. In Proc. International Conference on Computer Aided Design, Nov. 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. F. Li, G. Chen, M. Kandemir, and M. J. Irwin. Compiler-directed proactive power management for networks. In Proc. Conference on Compilers, Architectures and Synthesis of Embedded Systems, 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. R. Nagarajan, D. Burger, K. S. McKinley, C. Lin, S. W. Keckler, and S. K. Kushwaha. Static placement, dynamic issue (SPDI) scheduling for EDGE architectures. In Proc. International Conference on Parallel Architectures and Compilation Techniques, Oct. 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. L. M. Ni and P. K. McKinley. A survey of wormhole routing techniques in direct networks. Computer, 26(2):62--76, 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D. Burger, S. W. Keckler, and C. R. Moore. Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture. In Proc. the 30th Annual International Symposium on Computer Architecture, 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. L. Shang, L.-S. Peh, and N. K. Jha. Dynamic voltage scaling with links for power optimization of interconnection networks. In Proc. the International Symposium on High-Performance Computer Architecture, Feb. 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. T. Simunic and S. Boyd. Managing power consumption in networks on chip. In Proc. the Conference on Design, Automation and Test in Europe. IEEE Computer Society, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. V. Soteriou, N. Eisley, and L.-S. Peh. Software-directed poweraware interconnection networks. In Proc. Conference on Compilers, Architecture and Synthesis for Embedded Systems, Sept. 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. V. Soteriou and L.-S. Peh. Dynamic power management for power optimization of interconnection networks using on/off links. In Proc. 11th Symposium on High Performance Interconnects, 2003.Google ScholarGoogle ScholarCross RefCross Ref
  24. V. Soteriou and L.-S. Peh. Design space exploration of power-aware on/off interconnection networks. In Proc. the 22nd International Conference on Computer Design, Oct. 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. SUIF. Stanford university intermediate format. http://suif.stanford.edu/.Google ScholarGoogle Scholar
  26. C.-W. Tseng. An optimizing Fortran D compiler for MIMD distributed-memory machines. PhD thesis, Dept. of Computer Science, Rice University, TX, Jan. 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. R. von Hanxleden and K. Kennedy. A balanced code placement framework. ACM Trans. Program. Lang. Syst., 22(5):816--860, 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal. Baring it all to software: Raw machines. Computer, 30(9):86--93, 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. H.-S. Wang, X. Zhu, L.-S. Peh, and S. Malik. Orion: A power performance simulator for interconnection networks. In Proc. the 35th International Symposium on Microarchitecture, Nov. 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. M. E. Wolf, D. E. Maydan, and D.-K. Chen. Combining loop transformations considering caches and scheduling. In Proc. International Symposium on Microarchitecture, 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. F. Worm, P. Ienne, P. Thiran, and G. D. Micheli. An adaptive low power transmission scheme for on-chip networks. In Proc. the International System Synthesis Symposium, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. F. Xie, M. Martonosi, and S. Malik. Compile-time dynamic voltage scaling settings: Opportunities and limits. In Proc. the ACM SIGPLAN Conference on Programming Language Design and Implementation, June 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. N. D. Zervas, K. Masselos, and C. Goutis. Code transformations for embedded multimedia applications: impact on power and performance. In Proc. Power-Driven Microarchitecture Workshop, 1998.Google ScholarGoogle Scholar

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    • Published in

      cover image ACM Conferences
      PLDI '06: Proceedings of the 27th ACM SIGPLAN Conference on Programming Language Design and Implementation
      June 2006
      438 pages
      ISBN:1595933204
      DOI:10.1145/1133981
      • cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 41, Issue 6
        Proceedings of the 2006 PLDI Conference
        June 2006
        426 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/1133255
        Issue’s Table of Contents

      Copyright © 2006 ACM

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 11 June 2006

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      Overall Acceptance Rate406of2,067submissions,20%

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