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Effective compiler generation by architecture description

Published:14 June 2006Publication History

ABSTRACT

Embedded systems have an extremely short time to market and therefore require easily retargetable compilers. Architecture description languages (ADLs) provide a single concise architecture specification for the generation of hardware, instruction set simulators and compilers. In this article, we present an ADL for compiler generation. From a specification, we can derive an optimized tree pattern matching instruction selector, a register allocator and an instruction scheduler. Compared to a hand-crafted back end, the generated compiler produces smaller and faster code.The ADL is rich enough that other tools, such as assemblers, linkers, simulators and documentation, can all be obtained from a single specification.

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  • Published in

    cover image ACM Conferences
    LCTES '06: Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
    June 2006
    220 pages
    ISBN:159593362X
    DOI:10.1145/1134650
    • cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 41, Issue 7
      Proceedings of the 2006 LCTES Conference
      July 2006
      208 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/1159974
      Issue’s Table of Contents

    Copyright © 2006 ACM

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    • Published: 14 June 2006

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