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Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures

Published:14 June 2006Publication History

ABSTRACT

Reconfigurable architecture is one solution to the increasing computational requirement that often cannot be met by the low-end embedded processors. Compiling applications to such architectures involves hardware/software partitioning. To partition the applications, a set of parameters, such as the hardware execution time and hardware area consumption, is required for each application block. Quick derivation of the parameters for all the blocks is essential. Previous research has shown that the coarse-grained reconfigurable architectures are able to accelerate the applications. However, no research effort has been made to find the area and time for application blocks implemented on such architectures. In this paper we present an estimation model for the coarse-grained reconfigurable architectures implemented on FPGA platforms. The estimation model is able to quickly produce an area-time graph, which shows the area and time relationship, for each application block. The accuracy of the estimation model has been verified on real applications. Experiment shows that the estimation error for the area consumption is within 13% and the estimation error for the time is within 8%.

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  • Published in

    cover image ACM Conferences
    LCTES '06: Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
    June 2006
    220 pages
    ISBN:159593362X
    DOI:10.1145/1134650
    • cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 41, Issue 7
      Proceedings of the 2006 LCTES Conference
      July 2006
      208 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/1159974
      Issue’s Table of Contents

    Copyright © 2006 ACM

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    • Published: 14 June 2006

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