Abstract
Multiprocessor Systems on Chips (MPSoCs) have become a popular architectural technique to increase performance. However, MPSoCs may lead to undesirable power consumption characteristics for computing systems that have strict power budgets, such as PDAs, mobile phones, and notebook computers. This paper presents the super-complex instruction-set computing (SuperCISC) Embedded Processor Architecture and, in particular, investigates performance and power consumption of this device compared to traditional processor architecture-based execution. SuperCISC is a heterogeneous, multicore processor architecture designed to exceed performance of traditional embedded processors while maintaining a reduced power budget compared to low-power embedded processors. At the heart of the SuperCISC processor is a multicore VLIW (Very Large Instruction Word) containing several homogeneous execution cores/functional units. In addition, complex and heterogeneous combinational hardware function cores are tightly integrated to the core VLIW engine providing an opportunity for improved performance and reduced energy consumption. Our SuperCISC processor core has been synthesized for both a 90-nm Stratix II Field Programmable Gate Aray (FPGA) and a 160-nm standard cell Application-Specific Integrated Circuit (ASIC) fabrication process from OKI, each operating at approximately 167 MHz for the VLIW core. We examine several reasons for speedup and power improvement through the SuperCISC architecture, including predicated control flow, cycle compression, and a reduction in arithmetic power consumption, which we call power compression. Finally, testing our SuperCISC processor with multimedia and signal-processing benchmarks, we show how the SuperCISC processor can provide performance improvements ranging from 7X to 160X with an average of 60X, while also providing orders of magnitude of power improvements for the computational kernels. The power improvements for our benchmark kernels range from just over 40X to over 400X, with an average savings exceeding 130X. By combining these power and performance improvements, our total energy improvements all exceed 1000X. As these savings are limited to the computational kernels of the applications, which often consume approximately 90% of the execution time, we expect our savings to approach the ideal application improvement of 10X.
- Banerjee, P., Shenoy, N., Choudhary, A., Hauck, S., Bachmann, C., Chang, M., Haldar, M., Joisha, P., Jones, A., Kanhare, A., Nayak, A., Periyacheri, S., Walkden, M., and Zaretsky, D. 2000. A matlab compiler for distributed, heterogeneous, reconfigurable computing systems. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). Google Scholar
- Banerjee, P., Haldar, M., Nayak, A., Kim, V., Saxena, V., Parkes, S., Bagchi, D., Pal, S., Tripathi, N., Zaretsky, D., Anderson, R., and Uribe, J. 2004. Overview of a compiler for synthesizing matlab programs onto fpgas. IEEE Transactions on Very large Scale Integration (VLSI) Systems. Google Scholar
- Benini, L., Macii, A., Macii, E., and Poncino, M. 1999. Selective instruction compression for memory energy reduction in embedded systems. In Proceedings of the 1999 International Symposium on Low Power Electronics and Design. ACM Press, New York. 206--211. Google Scholar
- Callahan, T. J., Hauser, J. R., and Wawrzynek, J. 2000. The garp architecture and c compiler. Computer 33. Google Scholar
- Chandar, S., Mehendale, M., and Govindarajan, R. 2001. Area and power reduction of embedded dsp systems using instruction compression and reconfigurable encoding. In Proeedings of ICCAD. Google Scholar
- Chandrakasan, A., Sheng, S., and Brodersen, R. 1992. Low-power cmos digital design. JSSC 27, 4, 473--484.Google Scholar
- Chang, J.-M. and Pedram, M. 1996. Module assignment for low power. In European Design Automation Conference. Google Scholar
- Chen, Z. and Roy, K. 1998. A power macromodeling technique based on power sensitivity. In DAC '98: Proceedings of the 35th Annual Conference on Design Automation. ACM Press, New York. 678--683. Google Scholar
- Cousin, J.-G., Sentieys, O., and Chillet, D. 2000. Multi-algorithm asip synthesis and power estimation for dsp applications. In Proceedings of ISCAS.Google Scholar
- CoWare. The lisatek solution: Automated embedded processor design and software development tool generation. Datasheet, CoWare, Inc.Google Scholar
- Dutta, S., Wolfe, A., Wolf, W., and O'Connor, K. 1996. Design issues for very-long-instruction-word vlsi video signal processors. In IEEE Workshop on VLSI Signal Processing.Google Scholar
- Ebeling, C., Cronquist, D. C., and Franklin, P. 1996. Rapid - reconfigurable pipelined datapath. In in the 6th International Workshop on Field-Programmable Logic and Applications. Google Scholar
- eun Lee, J., Choi, K., and Dutt, N. D. 2003. Energy-efficient instruction set synthesis for application-specific processors. In Proceedings of ISLPED. ACM. Google Scholar
- Georing, R. 2000. Synopsys launches power tool. EETimes.Google Scholar
- Glokler, C. and Meyr, H. 2001. Power reduction for asips: A case study. In Proceedings of the Wkshp. Signal Processing Systems (SIPS).Google Scholar
- Gonzalez, R. E. 2000. Xtensa -- a configurable and extensible processor. IEEE Micro 20, 2, 60--70. Google Scholar
- Goodwin, D. and Petkov, D. 2003. Automatic generation of application specific processors. In Proceedings of the 2003 international conference on Compilers, Architectures and Synthesis for Embedded Systems. ACM Press, New York. 137--147. Google Scholar
- Gupta, S. and Najm, F. N. 1997. Power macromodeling for high level power estimation. In DAC '97: Proceedings of the 34th Annual Conference on Design Automation. ACM Press, New York. 365--370. Google Scholar
- Gupta, S., Gupta, R., Dutt, N., and Nicolau, A. 2004. SPARK: : A Parallelizing Approach to the High-Level Synthesis of Digital Circuits. Kluwer Academic Publishers, Boston, MA.Google Scholar
- Hauck, S., Fry, T. W., Hosler, M. M., and Kao, J. P. 1997. The chimaera reconfigurable functional unit. In IEEE Symposium on FPGAs for Custom Computing Machines(FCCM). 87--96. Google Scholar
- Hoare, R., Tung, S., and Werger, K. 2003. A 64-way simd processing architecture on an fpga. In IASTED International Conference on Parallel and Distributed Computing and Systems.Google Scholar
- Hoare, R., Tung, S., and Werger, K. 2004. An 88-way multiprocessor within an fpga with customizable instructions. In International Parallel and Distributed Processing Symposium (IPDPS).Google Scholar
- Hoare, R., Jones, A. K., Kusic, D., Fazekas, J., Foster, J., Tung, S., and McCloud, M. 2005. Rapid vliw processor customization for signal processing applications using combinational hardware functions. EURASIP Journal on Applied Signal Processing. Google Scholar
- Huang, Z. and Malik, S. 2002. Exploiting operation level parallelism through dynamicall reconfigurable datapaths. In Proc. of the Design Automation Conference (DAC). Google Scholar
- Huang, Z., Malik, S., Moreano, N., and Araujo, G. 2004. The design of dynamically reconfigurable datapath coprocessors. ACM Transactions on Embedded Computing Systems (TECS) 3, 2, 361--384. Google Scholar
- Jha, N. K. 2001. Low power system scheduling and synthesis. In Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design. IEEE Press, 259--263. Google Scholar
- Jones, A. K., Bagchi, D., Pal, S., Banerjee, P., and Choudhary, A. 2002. Pact HDL: Compiler Targeting ASIC's and FPGA's with Power and Performance Optimizations. Kluwer Academic Publishers, Boston, MA.Google Scholar
- Jones, A., Hoare, R., Kourtev, I., Fazekas, J., Kusic, D., Foster, J., Boddie, S., and Muaydh, A. 2004. A 64way vliw/simd fpga processing architecture and design flow. In IEEE International Conference on Electronics, Circuits, and Systems (ICECS).Google Scholar
- Jones, A. K., Hoare, R., Kusic, D., Fazekas, J., and Foster, J. 2005. An fpga-based vliw processor with custom hardware execution. In ACM International Symposium on Field-Programmable Gate Arrays (FPGA). Google Scholar
- Khailany, B. and et al. 2001. Imagine: media processing with streams. In Micro. Google Scholar
- Khailany, B., Dally, W. J., Chang, A., Kapsi, U. J., Namkoong, J., and Towles, B. 2002. Vlsi design and verification of the imagine processor. In IEEE International Conference on Computer Design (ICCD). Google Scholar
- Khouri, K., Lakshminarayana, G., and Jha, N. 1998. Impact: A highlevel synthesis system for low power control-flow intensive circuits. In Proc. Design Automation & Test in Europe Conf. 848--854. Google Scholar
- Lee, C., Potkonjak, M., and Magione-Smith, W. K. 1997. Mediabench: A tool for evaluating and synhesizing multimedia and communications systems. In Proceedings of the International Symposium on Microarchitecture. Google Scholar
- Levine, B. and Schmit, H. 2002. Piperench: Power & performance evaluation of a programmable pipelined datapath. presented at Hot Chips 14, Palo Alto, CA.Google Scholar
- Levine, B. A. and Schmit, H. 2003. Efficient application representation for haste: Hybrid architectures with a single, transformable executable. In IEEE Symposium on FPGAs for Custom Computing Machines(FCCM). Google Scholar
- Liu, X. and Papaefthymiou, M. C. 2001. A static power estimation methodology for ip-based design. In Design, Automation, and Test in Europe. 280--287. Google Scholar
- Liu, X. and Papaefthymiou, M. C. 2004. A markov chain sequence generator for power macromodeling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). Google Scholar
- McCloud, S. 2004. Catapult c synthesis-based design flow: Speeding implementation and increasing flexibility. Tech. rep., Mentor Graphics.Google Scholar
- Mehta, G., Jones, A. K., and Hoare, R. 2005. An energy-efficient coarse-grained reconfigurable fabric arch itecture. Tech. Rep. TR-ECE-2005-07-001, University of Pittsburgh, Department of Electrical and Computer Engineering. July.Google Scholar
- Mirsky, E. and Dehon, A. 1996. Matrix: A reconfigurable computing architecture with configurable instruction distribution and deployable resources. In in Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines.Google Scholar
- Musoll, E. and Cortadella, J. 1995. High-level synthesis techniques for reducing the activity of functional units. In Proceedings of the International Symposium on Low-Power Design. 99--104. Google Scholar
- Najm, F. N. 1994. A survey of power estimation techniques in vlsi circuits. IEEE Trans. Very Large Scale Integr. Syst. 2, 4, 446--455. Google Scholar
- Nene, A., Talla, S., Goldberg, B., Kim, H., and Rabbah, R. M. 1998. Trimaran: An infrastructure for compiler research in instruction level parallelism.Google Scholar
- Raghunathan, A. and Jha, N. K. 1994. Behavioral synthesis for low power. In Proceedings of ICCD. 318--322. Google Scholar
- Roy, K. and Prasad, S. 2000. Low-Power CMOS VLSI Design. Wiley, New York.Google Scholar
- Schmit, H., Whelihan, D., Tsai, A., Moe, M., Levine, B., and Taylor, R. R. 2002. Piperench: A virtualized programmable datapath in 0.18 micron technolog. In Proceedings of the IEEE Custom Integrated Circuits Conference.Google Scholar
- Shen, Z. X. and Jong, C. C. 1997. Exploring module selection space for architectural synthesis of low power designs. In IEEE International Symposium on Circuits and Systems.Google Scholar
- Sima, M., Cotofana, S., van Eijndhoven, J. T. J., Vassilidis, S., and Vissers, K. 2001. An 8 × 8 idct implementation on an fpga-augmented trimedia. In Field Programmable Custom Computing Machines (FCCM). Google Scholar
- Synopsys Inc. Design compiler and primepower manual. www.synopsys.com.Google Scholar
- Tang, X., Jiang, T., Jones, A. K., and Banerjee, P. 2005. Behavioral synthesis of data-dominated circuits for minimal energy implementation. In Proceedings of the IEEE International Conference on VLSI Design. Google Scholar
Index Terms
Reducing power while increasing performance with supercisc
Recommendations
Increasing the number of effective registers in a low-power processor using a windowed register file
CASES '03: Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systemsLow-power embedded processors utilize compact instruction encodings to achieve small code size. Instruction sizes of 8 to 16 bits are common. Such encodings place tight restrictions on the number of bits available to encode operand specifiers, and thus ...
An FPGA-based VLIW processor with custom hardware execution
FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arraysThe capability and heterogeneity of new FPGA (Field Programmable Gate Array) devices continues to increase with each new line of devices. Efficiently programming these devices is increasing in difficulty. However, FPGAs continue to be utilized for ...
High-Level Design Synthesis of a Low Power, VLIW Processor for the IS-54 VSELP Speech Encoder
ICCD '97: Proceedings of the 1997 International Conference on Computer Design (ICCD '97)General purpose DSPs typically used to implement speech coders in digital cellular phones do not allow enough exploitation of the speech coding algorithm itself for power reduction. In this paper, high-level design synthesis of a low power, VLIW (very ...






Comments