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VISTA: VPO interactive system for tuning applications

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Published:01 November 2006Publication History
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Abstract

Software designers face many challenges when developing applications for embedded systems. One major challenge is meeting the conflicting constraints of speed, code size, and power consumption. Embedded application developers often resort to hand-coded assembly language to meet these constraints since traditional optimizing compiler technology is usually of little help in addressing this challenge. The results are software systems that are not portable, less robust, and more costly to develop and maintain. Another limitation is that compilers traditionally apply the optimizations to a program in a fixed order. However, it has long been known that a single ordering of optimization phases will not produce the best code for every application. In fact, the smallest unit of compilation in most compilers is typically a function and the programmer has no control over the code improvement process other than setting flags to enable or disable certain optimization phases. This paper describes a new code improvement paradigm implemented in a system called VISTA that can help achieve the cost/performance trade-offs that embedded applications demand. The VISTA system opens the code improvement process and gives the application programmer, when necessary, the ability to finely control it. VISTA also provides support for finding effective sequences of optimization phases. This support includes the ability to interactively get static and dynamic performance information, which can be used by the developer to steer the code improvement process. This performance information is also internally used by VISTA for automatically selecting the best optimization sequence from several attempted. One such feature is the use of a genetic algorithm to search for the most efficient sequence based on specified fitness criteria. We include a number of experimental results that evaluate the effectiveness of using a genetic algorithm in VISTA to find effective optimization phase sequences.

References

  1. Andrews, K., Henry, R., and Yamamoto, W. 1988. Design and implementation of the UW illustrated compiler. In ACM SIGPLAN Conference on Programming Language Design and Implementation. 105--114. Google ScholarGoogle Scholar
  2. Appelbe, B., Smith, K., and McDowell, C. 1989. Start/pat: A parallel---programming toolkit. In IEEE Software. 4, 6, 29--40. Google ScholarGoogle Scholar
  3. Benitez, M. E. and Davidson, J. W. 1988. A portable global optimizer and linker. In Proceedings of the SIGPLAN'88 conference on Programming Language Design and Implementation. ACM Press, New York. 329--338. Google ScholarGoogle Scholar
  4. Benitez, M. E. and Davidson, J. W. 1994. The advantages of machine-dependent global optimization. In Proceedings of the 1994 International Conference on Programming Languages and Architectures. 105--124. Google ScholarGoogle Scholar
  5. Boyd, M. and Whalley, D. 1993. Isolation and analysis of optimization errors. In ACM SIGPLAN Conference on Programming Language Design and Implementation. 26--35. Google ScholarGoogle Scholar
  6. Boyd, M. and Whalley, D. 1995. Graphical visualization of compiler optimizations. Programming Languages 3, 69--94.Google ScholarGoogle Scholar
  7. Browne, J., Sridharan, K., Kiall, J., Denton, C., and Eventoff, W. 1990. Parallel structuring of real-time simulation programs. In COMPCON Spring '90: Thirty-Fifth IEEE Computer Society International Conference. 580--584.Google ScholarGoogle Scholar
  8. Burger, D. and Austin, T. M. 1997. The SimpleScalar tool set, version 2.0. SIGARCH Comput. Archit. News 25, 3, 13--25. Google ScholarGoogle Scholar
  9. Chow, K. and Wu, Y. 1999. Feedback-directed selection and characterization of compiler optimizations. In Workshop on Feedback-Directed Optimization.Google ScholarGoogle Scholar
  10. Cooper, K. D., Schielke, P. J., and Subramanian, D. 1999. Optimizing for reduced code space using genetic algorithms. In Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems. ACM Press, New York. 1--9. Google ScholarGoogle Scholar
  11. Davidson, J. W. and Whalley, D. B. 1989. Quick compilers using peephole optimization. Software---Practice and Experience 19, 1, 79--97. Google ScholarGoogle Scholar
  12. Davidson, J. W. and Whalley, D. B. 1991. A design environment for addressing architecture and compiler interactions. Microprocessors and Microsystems 15, 9 (Nov.), 459--472.Google ScholarGoogle Scholar
  13. Dow, C.-R., Chang, S.-K., and Soffa, M. L. 1992. A visualization system for parallelizing programs. In Supercomputing. 194--203. Google ScholarGoogle Scholar
  14. Granlund, T. and Kenner, R. 1992. Eliminating branches using a superoptimizer and the GNU C compiler. In Proceedings of the SIGPLAN '92 Conference on Programming Language Design and Implementation. 341--352. Google ScholarGoogle Scholar
  15. Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin, T. M., Mudge, T., and Brown, R. B. 2001. MiBench: A free, commercially representative embedded benchmark suite. IEEE 4th Annual Workshop on Workload Characterization. Google ScholarGoogle Scholar
  16. Harvey, B. and Tyson, G. 1996. Graphical user interface for compiler optimizations with Simple-SUIF. Technical Report UCR-CS-96-5, Department of Computer Science, University of California Riverside, Riverside, CA.Google ScholarGoogle Scholar
  17. Kisuki, T., Knijnenburg, P. M. W., and O'Boyle, M. F. P. 2000. Combined selection of tile sizes and unroll factors using iterative compilation. In IEEE PACT. 237--248. Google ScholarGoogle Scholar
  18. Knijnenburg, P., Kisuki, T., Gallivan, K., and O'Boyle, M. 2000. The effect of cache models on iterative compilation for combined tiling and unrolling. In Proc. FDDO-3. 31--40.Google ScholarGoogle Scholar
  19. Kulkarni, P., Zhao, W., Moon, H., Cho, K., Whalley, D., Davidson, J., Bailey, M., Paek, Y., and Gallivan, K. 2003. Finding effective optimization phase sequences. In Proceedings of the 2003 ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems. ACM Press, New York. 12--23. Google ScholarGoogle Scholar
  20. Kulkarni, P., Hines, S., Hiser, J., Whalley, D., Davidson, J., and Jones, D. 2004. Fast searches for effective optimization phase sequences. In Proceedings of the ACM SIGPLAN '04 Conference on Programming Language Design and Implementation. Google ScholarGoogle Scholar
  21. Liao, S.-W., Diwan, A., Robert P. Bosch, J., Ghuloum, A., and Lam, M. S. 1999. SUIF Explorer: An interactive and interprocedural parallelizer. In Proceedings of the seventh ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. ACM Press, New York. 37--48. Google ScholarGoogle Scholar
  22. Marwedel, P. and Goossens, G. 1995. Code Generation for Embedded Processors. Kluwer Academic Publishers, Boston, MA. Google ScholarGoogle Scholar
  23. Massalin, H. 1987. Superoptimizer: A look at the smallest program. In Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems. 122--126. Google ScholarGoogle Scholar
  24. Nisbet, A. 1998. Genetic algorithm optimized parallelization. In Workshop on Profile and Feedback Directed Compilation.Google ScholarGoogle Scholar
  25. Novack, S. and Nicolau, A. 1993. VISTA: The visual interface for scheduling transformations and analysis. In Languages and Compilers for Parallel Computing. 449--460. Google ScholarGoogle Scholar
  26. Polychronopoulos, C., Girkar, M., Haghighat, M., Lee, C., Leung, B., and Schouten, D. 1989. Parafrase--2: An environment for parallelizing, partitioning, and scheduling programs on multiprocessors. In International Journal of High Speed Computing. 1, vol. 1. Pennsylvania State University Press, 39--48. Google ScholarGoogle Scholar
  27. Vegdahl, S. R. 1982. Phase coupling and constant generation in an optimizing microcode compiler. In Proceedings of the Fifteenth Annual Workshop on Microprogramming. 125--133. Google ScholarGoogle Scholar
  28. Whaley, R., Petitet, A., and Dongarra, J. 2001. Automated empirical optimization of software and the ATLAS project. In Parallel Computing. 1-2, vol. 27. 3--25.Google ScholarGoogle Scholar
  29. Whitfield, D. L. and Soffa, M. L. 1997. An approach for exploring code improving transformations. ACM Transactions on Programming Languages and Systems (TOPLAS) 19, 6, 1053--1084. Google ScholarGoogle Scholar
  30. Zhao, W., Cai, B., Whalley, D., Bailey, M. W., van Engelen, R., Yuan, X., Hiser, J. D., Davidson, J. W., Gallivan, K., and Jones, D. L. 2002. VISTA: a system for interactive code improvement. In Proceedings of the Joint Conference on Languages, Compilers and Tools for Embedded Systems. ACM Press, New York. 155--164. Google ScholarGoogle Scholar
  31. Zhao, W., Kulkarni, P., Whalley, D., Healy, C., Mueller, F., and Uh, G.-R. 2004. Tuning the wcet of embedded applications. In 10th IEEE Real-Time and Embedded Technology and Applications Symposium. Google ScholarGoogle Scholar

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