skip to main content
article

Offset assignment using simultaneous variable coalescing

Published:01 November 2006Publication History
Skip Abstract Section

Abstract

The generation of efficient addressing code is a central problem in compiling for processors with restricted addressing modes, like digital signal processors (DSPs). Offset assignment (OA) is the problem of allocating scalar variables to memory, so as to minimize the need of addressing instructions. This problem is called simple offset assignment (SOA) when a single address register is available, and general offset assignment (GOA) when more address registers are used. This paper shows how variables' liveness information can be used to dramatically reduce the addressing instructions required to access local variables on the program stack. Two techniques that make effective use of variable coalescing to solve SOA and GOA are described, namely coalescing SOA (CSOA) and coalescing GOA (CGOA). In addition, a thorough comparison between these algorithms and others described in the literature is presented. The experimental results, when compiling MediaBench benchmark programs with the LANCE compiler, reveal a very significant improvement of the proposed techniques over the other available solutions to the problem.

References

  1. Aho, A. V., Sethi, R., and Ullman, J. D. 1986. Compilers: Principles,Techinques and Tools. Addison-Wesley, Reading, MA.]] Google ScholarGoogle Scholar
  2. Araujo, G., Sudarsanam, A., and Malik, S. 1996. Instruction set design and optimizations for address computation in dsp architectures. In Proc. of the 9th. ACM/IEEE International Symposium on System Synthesis. 102--107.]] Google ScholarGoogle Scholar
  3. Atri, S., Ramanujam, J., and Kandemir, M. 2001. Improving offset assignment for embedded processors. Lecture Notes in Computer Science 2017.]] Google ScholarGoogle Scholar
  4. Bartley, D. H. 1992. Optimizing stack frame accesses for processors with restricted addressing modes. Software---Practice and Experience 22, 2, 101--110.]] Google ScholarGoogle Scholar
  5. Briggs, P. 1992. Register allocation via graph coloring. Ph.D. thesis, Rice University.]] Google ScholarGoogle Scholar
  6. Chaitin, G. J. 1982. Register allocation and spilling via graph coloring. In Proc. of the ACM SIGPLAN'82 Symposium on Compiler Construction.]] Google ScholarGoogle Scholar
  7. Choi, Y. and Kim, T. 2002. Address assignment combined with scheduling in DSP code generation. In Proc. of the 39th Design Automation Conference, DAC 2002.]] Google ScholarGoogle Scholar
  8. Cintra, M. and Araujo, G. 2000. Array reference allocation using ssaform and live range growth. In Proc. of the ACM SIGPLAN 2000 LCTES. 26--33.]] Google ScholarGoogle Scholar
  9. Cormen, T. H., Leiserson, C. E., and Rivest, R. L. 1990. Introduction to Algorithms. The MIT Press and McGraw-Hill, Cambridge, MA and New York.]] Google ScholarGoogle Scholar
  10. Eckstein, E. and Krall, A. 1999. Minimizing cost of local variables access for DSP-processors. In Proc. of the ACM SIGPLAN 1999 LCTES.]] Google ScholarGoogle Scholar
  11. George, L. and Appel, A. 1996. Iterated register coalescing. In Proceedings of the 23th ACM Symposium on Principles of Programming Languages. 208--218.]] Google ScholarGoogle Scholar
  12. Lee, C., Potkonjak, M., and Mangione-Smith, W. H. 1997. Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In Proc. of the 30th Annual International Symposium on Microarchitecture (Micro 30).]] Google ScholarGoogle Scholar
  13. Leupers, R. 2000. Code Optimization for Embedded Processors. Kluwer Academic Publ., Boston, MA.]] Google ScholarGoogle Scholar
  14. Leupers, R. 2001. Lance: A c compiler platform for embedded processors. In Embedded Systems/Embedded Intelligence.]]Google ScholarGoogle Scholar
  15. Leupers, R. 2003. Offset assignment showdown: Evaluation of DSP address code optimization algorithms. In Proceedings of the 12th International Conference on Compiler Construction.]]Google ScholarGoogle Scholar
  16. Leupers, R. and David, F. 1998. A uniform optimization technique for offset assignment problems. In Proc. of the International Symposium on System Synthesis (ISSS). 3--8.]] Google ScholarGoogle Scholar
  17. Leupers, R. and Marwedel, P. 1996. Algorithms for address assignment in DSP code generation. In International Conference on Computer-Aided Design (ICCAD). 109--112.]] Google ScholarGoogle Scholar
  18. Leupers, R., Basu, A., and Marwedel, P. 1998. Optimized array index computation in DSP programs. In Proc. of the Asia South Pacific Design Automation Conference (ASP-DAC). IEEE.]]Google ScholarGoogle Scholar
  19. Li, B. and Gupta, R. 2003. Simple offset assignment in precense of subword data. In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES'03). ACM Press, New York. 12--23.]] Google ScholarGoogle Scholar
  20. Liao, S. 1996. Code generation and optimization for embedded digital signal processors. Ph.D. thesis, Massachusetts Institute of Technology.]] Google ScholarGoogle Scholar
  21. Liao, S., Devadas, S., Keutzer, K., Tjiang, S., and Wang, A. 1996. Storage assignment to decrease code size. ACM Transactions on Programming Languages and Systems 18, 3 (May), 235--253.]] Google ScholarGoogle Scholar
  22. Muchnick, S. S. 1997. Advanced Compiler Design and Implementation. Morgan Kaufmann, San Mateo, CA.]] Google ScholarGoogle Scholar
  23. Ottoni, G. and Araujo, G. 2003. Address register allocation for arrays in loops of embedded programs. Microelectronics Journal 34, 11 (Oct.), 1009--1018.]]Google ScholarGoogle Scholar
  24. Ottoni, G., Rigo, S., Araujo, G., Rajagopalan, S., and Malik, S. 2001. Optimal live range merge for address register allocation in embedded programs. In Proceedings of the 10th International Conference on Compiler Construction, CC2001, LNCS 2027. Springer, New York. 274--288.]] Google ScholarGoogle Scholar
  25. Ottoni, D., Ottoni, G., Ara&jdot;o, G., and Leupers, R. 2003. Offset assignment through simultaneous variable coalescing. In Proceedings of the 7th International Workshop on Software and Compilers for Embedded Systems (SCOPES'03). Vol. LNCS 2826. Springer Verlag, New York. 285--297.]]Google ScholarGoogle Scholar
  26. Rao, A. and Pande, S. 1999. Storage assignment optimizations to gerenrate compact and efficient code on embedded dsps. In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI'99). 128--138.]] Google ScholarGoogle Scholar
  27. Sudarsanam, A., Liao, S., and Devadas, S. 1997. Analysis and evaluation of address arithmetic capabilities in custom DSP architectures. In Design Automation Conference. 287--292.]] Google ScholarGoogle Scholar
  28. Udayanarayanan, S. and Chakrabarti, C. 2001. Address code generation for digital signal processors. In Proceedings of ACM/IEEE Design Automation Conference (DAC'01). 155--164.]] Google ScholarGoogle Scholar
  29. West, D. B. 2001. Introduction to Graph Theory, 2nd ed. Prentice Hall, Englewood Cliffs, NJ.]]Google ScholarGoogle Scholar
  30. Zhuang, X., Lau, C., and Pande, S. 2003. Storage assignment optimizations through variable coalescence for embedded processors. In Proceedings of the 2003 ACM SIGPLAN Conference on Languages, Compilers and Tools for Embedded Processors (LCTES'03). ACM Press, New York. 220--231.]] Google ScholarGoogle Scholar

Index Terms

  1. Offset assignment using simultaneous variable coalescing

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in

    Full Access

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader
    About Cookies On This Site

    We use cookies to ensure that we give you the best experience on our website.

    Learn more

    Got it!