Abstract
The current literature is filled with descriptions of various microprogrammed processors and discussions of the improvements in performance that can be realized through microprogramming. Thus, Tucker and Flynn [1] describe a dynamically microprogrammed processor and give several examples of problem-oriented programming in which the performance of the microcode was much better than that of assembly language code (System/360, normalized technology). Recently, Abd-alla and Karlgaard [2] have developed an algorithm for the synthesis of applications-oriented microcode for a dynamically microprogrammed computer. Their paper gives examples of problem-oriented architectures (realized through specialized instruction sets) which have much better performance than the corresponding general purpose architectures. This trend toward realizing specialized computer systems by means of writable control store probably means that more people will be writing microcode in the future. In particular, it seems worthwhile to consider the relation of the instruction sequencing functions of a given machine to both the ease of writing correct microcode and the size of control memory required for that machine. So far there seems to have been little or no discussion of this topic in the literature [3].
- Tucker, A. B., and Flynn, M. J., "Dynamic Microprogramming: Processor Organization and Programming," Comm. of the ACM, 14 (April 1971), pp. 240--250. Google Scholar
Digital Library
- Abd-alla, A. M., and Karlgaard, D. C., "The Heuristic Synthesis of Applications-Oriented Microcode", Sixth Workshop on Microprogramming, College Park, Maryland (Sept. 1973) (Preprints). Google Scholar
Digital Library
- Jones, L. H., et. al., "An Annotated Bibliography on Microprogramming-I, and II," SIGMICRO Newsletter, 3 (July 1972) No. 2, pp. 39--55; and 4 (July 1973) No. 2. Google Scholar
Digital Library
- Roberts, J. D., Jr., Ihnat, J., and Smith, W. R., Jr., "Microprogrammed Control Unit (MCU) Programming Reference Manual," SIGMICRO Newsletter, 3 (Oct. 1972), No. 3, pp. 18--57.Google Scholar
Digital Library
- Mills, Harlan, "Mathematical Foundations for Structured Programming," IBM Research Report FSC 72-6012 (February 1972).Google Scholar
- Reigel, E. W., Faber, U., and Fisher, D. A., "The Interpreter--A Microprogrammable Building Block System," AFIPS Conference Proceedings, 40, (SJCC 1972), pp. 705--723.Google Scholar
- Fisher, D. A., "Control Structures for Programming Languages," Ph. D. Dissertation, Carnegie-Mellon University, May 1970. Google Scholar
Digital Library
Recommendations
Increasing the instruction fetch rate via block-structured instruction set architectures
MICRO 29: Proceedings of the 29th annual ACM/IEEE international symposium on MicroarchitectureTo exploit larger amounts of instruction level parallelism, processors are being built with wider issue widths and larger numbers of functional units. Instruction fetch rate must also be increased in order to effectively exploit the performance ...
Microprogramming instruction systolic arrays
The instruction systolic array (ISA) is a programmable parallel architecture suitable for VLSI implementation. This paper presents a generalization of the ISA, called the microprogrammed ISA, which uses simple microprogramming techniques. ...






Comments