Abstract
SLIM (Stanford Language for Implementing Microcode) is a programming language based system for specifying and simulating microcode in a VLSI chip. The language is oriented towards PLA implementations of microcoded machines using either a microprogram counter or a finite state machine. The SLIM system supports simulation of the microcode and will drive a PLA layout program to automatically create the PLA.
- Clark, J. H. "A VLSI Geometry Processor for Graphics." Computer 13, 7 (July 1980), 59--68.Google Scholar
Digital Library
- Clark, J. H. and Hannah, M. R. "Distributed Processing in a High-Performance Smart Image Memory." Lambda 1, 3 (1980), 40--45.Google Scholar
- Duley, J. R. and Dictmeyer, D. L. "Translation of DDL digital system specification to Boolean equations." IEEE Trans. Computers 18, 4 (April 1969), 305--313.Google Scholar
- Hennessy, J. L., Clark, J. H., and Hannah, M. R. A comparasion of two different VLSI control structures.Google Scholar
- Holloway J., Steele, G., Sussman, G., Bell, A. The Scheme-79 Chip. Tech. Rept. 599, Artificial Intelligence Laboratory, MIT, January, 1980.Google Scholar
- Mead, C. and Conway, L. Introduction to VLSI Systems. Addison-Wesley, Menlo Park, Ca., 1980. Google Scholar
Digital Library
- Weber, H. High Level Design for Programmed Logic Arrays. Proceedings of Fourth Conf. on Computer Hardware Description Languages, May, 1979, pp. 96--101.Google Scholar
Recommendations
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs
VLSID '97: Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia ApplicationsAn exclusive-OR transform of input variables significantly reduces the size of the PLA implementation for adder and comparator circuits. For n bit adder circuits, the size of PLA for transformed functions is O(n/sup 2/). In comparison, when the complete ...
A 20 Bit Logarithmic Number System Processor
The architecture and performance of a 20-bit arithmetic processor based on the logarithmic number system (LNS) is described. The processor performed LNS multiplication and division rapidly and with a low hardware complexity. Addition and subtraction in ...
Block-Level Relaxation for Timing-Robust Asynchronous Circuits Based on Eager Evaluation
ASYNC '08: Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and SystemsAs variability and timing closure become critical challenges in synchronous CAD flows, one attractive alternative is to use robust asynchronous circuits which gracefully accommodate timing discrepancies. In this approach, each gate in an initial Boolean ...






Comments