ABSTRACT
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multi-processor architecture in a locality-aware fashion. The proposed compiler approach has four major steps: task scheduling, processor mapping, data mapping, and packet routing. Our experimental result clearly shows that the proposed framework reduces energy consumption of our applications significantly (27.41% on average over a pure performance oriented application mapping strategy) as a result of improved locality of data accesses.
- J. M. Anderson. Automatic Computation and Data Decomposition for Multiprocessors. Ph.D. Thesis, Computer Science Department, Stanford University, March 1997. Google Scholar
Digital Library
- L. Benini and G. D. Micheli. Powering NoCs: energy-efficient and reliable interconnect design for SoCs. In Proc. ISSS, 2001. Google Scholar
Digital Library
- G. Chen, F. Li, and M. Kandemir. Compiler-directed channel allocation for saving power in on-chip networks. In Proc. POPL, Charleston, SC, Jan. 2006. Google Scholar
Digital Library
- W. J. Dally and B. Towles. Route packets, not wires: on-chip interconnection networks. In Proc. DAC, Las Vegas, NV, June 2001. Google Scholar
Digital Library
- Virtutech Simics: http://www.virtutech.com/Google Scholar
- H.-S. Wang, X. Zhu, L.-S. Peh, and S. Malik. Orion: A power-performance simulator for interconnection networks. In Proc. MICRO, Nov. 2002. Google Scholar
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Index Terms
Compiler-directed application mapping for NoC based chip multiprocessors
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