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Code and data partitioning for fine-grain parallelism

Published:13 June 2007Publication History
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References

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  7. TAYLOR, M., LEE, W., AMARASI NGHE, S., AND AGARWAL, A. Scalar operand networks: On-chip interconnect for ILP in partitioned architectures. In Proc. of the 9th International Symposium on High-Performance Computer Architecture (Feb. 2003), pp. 341--353. Google ScholarGoogle ScholarDigital LibraryDigital Library

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        • Published in

          cover image ACM Conferences
          LCTES '07: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
          June 2007
          258 pages
          ISBN:9781595936325
          DOI:10.1145/1254766
          • cover image ACM SIGPLAN Notices
            ACM SIGPLAN Notices  Volume 42, Issue 7
            Proceedings of the 2007 LCTES conference
            July 2007
            241 pages
            ISSN:0362-1340
            EISSN:1558-1160
            DOI:10.1145/1273444
            Issue’s Table of Contents

          Copyright © 2007 ACM

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          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 13 June 2007

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